arch/arm/boot/dts/aspeed-g5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 #include <dt-bindings/clock/aspeed-clock.h>
   3
   4 / {
   5         model = "Aspeed BMC";
   6         compatible = "aspeed,ast2500";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 i2c0 = &i2c0;
  13                 i2c1 = &i2c1;
  14                 i2c2 = &i2c2;
  15                 i2c3 = &i2c3;
  16                 i2c4 = &i2c4;
  17                 i2c5 = &i2c5;
  18                 i2c6 = &i2c6;
  19                 i2c7 = &i2c7;
  20                 i2c8 = &i2c8;
  21                 i2c9 = &i2c9;
  22                 i2c10 = &i2c10;
  23                 i2c11 = &i2c11;
  24                 i2c12 = &i2c12;
  25                 i2c13 = &i2c13;
  26                 serial0 = &uart1;
  27                 serial1 = &uart2;
  28                 serial2 = &uart3;
  29                 serial3 = &uart4;
  30                 serial4 = &uart5;
  31                 serial5 = &vuart;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         compatible = "arm,arm1176jzf-s";
  40                         device_type = "cpu";
  41                         reg = <0>;
  42                 };
  43         };
  44
  45         memory@80000000 {
  46                 device_type = "memory";
  47                 reg = <0x80000000 0>;
  48         };
  49
  50         ahb {
  51                 compatible = "simple-bus";
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges;
  55
  56                 fmc: flash-controller@1e620000 {
  57                         reg = < 0x1e620000 0xc4
  58                                 0x20000000 0x10000000 >;
  59                         #address-cells = <1>;
  60                         #size-cells = <0>;
  61                         compatible = "aspeed,ast2500-fmc";
  62                         clocks = <&syscon ASPEED_CLK_AHB>;
  63                         status = "disabled";
  64                         interrupts = <19>;
  65                         flash@0 {
  66                                 reg = < 0 >;
  67                                 compatible = "jedec,spi-nor";
  68                                 status = "disabled";
  69                         };
  70                         flash@1 {
  71                                 reg = < 1 >;
  72                                 compatible = "jedec,spi-nor";
  73                                 status = "disabled";
  74                         };
  75                         flash@2 {
  76                                 reg = < 2 >;
  77                                 compatible = "jedec,spi-nor";
  78                                 status = "disabled";
  79                         };
  80                 };
  81
  82                 spi1: flash-controller@1e630000 {
  83                         reg = < 0x1e630000 0xc4
  84                                 0x30000000 0x08000000 >;
  85                         #address-cells = <1>;
  86                         #size-cells = <0>;
  87                         compatible = "aspeed,ast2500-spi";
  88                         clocks = <&syscon ASPEED_CLK_AHB>;
  89                         status = "disabled";
  90                         flash@0 {
  91                                 reg = < 0 >;
  92                                 compatible = "jedec,spi-nor";
  93                                 status = "disabled";
  94                         };
  95                         flash@1 {
  96                                 reg = < 1 >;
  97                                 compatible = "jedec,spi-nor";
  98                                 status = "disabled";
  99                         };
 100                 };
 101
 102                 spi2: flash-controller@1e631000 {
 103                         reg = < 0x1e631000 0xc4
 104                                 0x38000000 0x08000000 >;
 105                         #address-cells = <1>;
 106                         #size-cells = <0>;
 107                         compatible = "aspeed,ast2500-spi";
 108                         clocks = <&syscon ASPEED_CLK_AHB>;
 109                         status = "disabled";
 110                         flash@0 {
 111                                 reg = < 0 >;
 112                                 compatible = "jedec,spi-nor";
 113                                 status = "disabled";
 114                         };
 115                         flash@1 {
 116                                 reg = < 1 >;
 117                                 compatible = "jedec,spi-nor";
 118                                 status = "disabled";
 119                         };
 120                 };
 121
 122                 vic: interrupt-controller@1e6c0080 {
 123                         compatible = "aspeed,ast2400-vic";
 124                         interrupt-controller;
 125                         #interrupt-cells = <1>;
 126                         valid-sources = <0xfefff7ff 0x0807ffff>;
 127                         reg = <0x1e6c0080 0x80>;
 128                 };
 129
 130                 mac0: ethernet@1e660000 {
 131                         compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
 132                         reg = <0x1e660000 0x180>;
 133                         interrupts = <2>;
 134                         clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
 135                         status = "disabled";
 136                 };
 137
 138                 mac1: ethernet@1e680000 {
 139                         compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
 140                         reg = <0x1e680000 0x180>;
 141                         interrupts = <3>;
 142                         clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
 143                         status = "disabled";
 144                 };
 145
 146                 ehci0: usb@1e6a1000 {
 147                         compatible = "aspeed,ast2500-ehci", "generic-ehci";
 148                         reg = <0x1e6a1000 0x100>;
 149                         interrupts = <5>;
 150                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 151                         status = "disabled";
 152                 };
 153
 154                 ehci1: usb@1e6a3000 {
 155                         compatible = "aspeed,ast2500-ehci", "generic-ehci";
 156                         reg = <0x1e6a3000 0x100>;
 157                         interrupts = <13>;
 158                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
 159                         status = "disabled";
 160                 };
 161
 162                 uhci: usb@1e6b0000 {
 163                         compatible = "aspeed,ast2500-uhci", "generic-uhci";
 164                         reg = <0x1e6b0000 0x100>;
 165                         interrupts = <14>;
 166                         #ports = <2>;
 167                         clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
 168                         status = "disabled";
 169                 };
 170
 171                 apb {
 172                         compatible = "simple-bus";
 173                         #address-cells = <1>;
 174                         #size-cells = <1>;
 175                         ranges;
 176
 177                         syscon: syscon@1e6e2000 {
 178                                 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
 179                                 reg = <0x1e6e2000 0x1a8>;
 180                                 #address-cells = <1>;
 181                                 #size-cells = <0>;
 182                                 #clock-cells = <1>;
 183                                 #reset-cells = <1>;
 184
 185                                 pinctrl: pinctrl {
 186                                         compatible = "aspeed,g5-pinctrl";
 187                                         aspeed,external-nodes = <&gfx &lhc>;
 188
 189                                 };
 190                         };
 191
 192                         rng: hwrng@1e6e2078 {
 193                                 compatible = "timeriomem_rng";
 194                                 reg = <0x1e6e2078 0x4>;
 195                                 period = <1>;
 196                                 quality = <100>;
 197                         };
 198
 199                         gfx: display@1e6e6000 {
 200                                 compatible = "aspeed,ast2500-gfx", "syscon";
 201                                 reg = <0x1e6e6000 0x1000>;
 202                                 reg-io-width = <4>;
 203                         };
 204
 205                         adc: adc@1e6e9000 {
 206                                 compatible = "aspeed,ast2500-adc";
 207                                 reg = <0x1e6e9000 0xb0>;
 208                                 clocks = <&syscon ASPEED_CLK_APB>;
 209                                 resets = <&syscon ASPEED_RESET_ADC>;
 210                                 #io-channel-cells = <1>;
 211                                 status = "disabled";
 212                         };
 213
 214                         sram@1e720000 {
 215                                 compatible = "mmio-sram";
 216                                 reg = <0x1e720000 0x9000>;      // 36K
 217                         };
 218
 219                         gpio: gpio@1e780000 {
 220                                 #gpio-cells = <2>;
 221                                 gpio-controller;
 222                                 compatible = "aspeed,ast2500-gpio";
 223                                 reg = <0x1e780000 0x1000>;
 224                                 interrupts = <20>;
 225                                 gpio-ranges = <&pinctrl 0 0 220>;
 226                                 clocks = <&syscon ASPEED_CLK_APB>;
 227                                 interrupt-controller;
 228                         };
 229
 230                         timer: timer@1e782000 {
 231                                 /* This timer is a Faraday FTTMR010 derivative */
 232                                 compatible = "aspeed,ast2400-timer";
 233                                 reg = <0x1e782000 0x90>;
 234                                 interrupts = <16 17 18 35 36 37 38 39>;
 235                                 clocks = <&syscon ASPEED_CLK_APB>;
 236                                 clock-names = "PCLK";
 237                         };
 238
 239                         uart1: serial@1e783000 {
 240                                 compatible = "ns16550a";
 241                                 reg = <0x1e783000 0x20>;
 242                                 reg-shift = <2>;
 243                                 interrupts = <9>;
 244                                 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
 245                                 resets = <&lpc_reset 4>;
 246                                 no-loopback-test;
 247                                 status = "disabled";
 248                         };
 249
 250                         uart5: serial@1e784000 {
 251                                 compatible = "ns16550a";
 252                                 reg = <0x1e784000 0x20>;
 253                                 reg-shift = <2>;
 254                                 interrupts = <10>;
 255                                 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
 256                                 no-loopback-test;
 257                                 status = "disabled";
 258                         };
 259
 260                         wdt1: watchdog@1e785000 {
 261                                 compatible = "aspeed,ast2500-wdt";
 262                                 reg = <0x1e785000 0x20>;
 263                                 clocks = <&syscon ASPEED_CLK_APB>;
 264                         };
 265
 266                         wdt2: watchdog@1e785020 {
 267                                 compatible = "aspeed,ast2500-wdt";
 268                                 reg = <0x1e785020 0x20>;
 269                                 clocks = <&syscon ASPEED_CLK_APB>;
 270                         };
 271
 272                         wdt3: watchdog@1e785040 {
 273                                 compatible = "aspeed,ast2500-wdt";
 274                                 reg = <0x1e785040 0x20>;
 275                                 clocks = <&syscon ASPEED_CLK_APB>;
 276                                 status = "disabled";
 277                         };
 278
 279                         pwm_tacho: pwm-tacho-controller@1e786000 {
 280                                 compatible = "aspeed,ast2500-pwm-tacho";
 281                                 #address-cells = <1>;
 282                                 #size-cells = <0>;
 283                                 reg = <0x1e786000 0x1000>;
 284                                 clocks = <&syscon ASPEED_CLK_APB>;
 285                                 resets = <&syscon ASPEED_RESET_PWM>;
 286                                 status = "disabled";
 287                         };
 288
 289                         vuart: serial@1e787000 {
 290                                 compatible = "aspeed,ast2500-vuart";
 291                                 reg = <0x1e787000 0x40>;
 292                                 reg-shift = <2>;
 293                                 interrupts = <8>;
 294                                 clocks = <&syscon ASPEED_CLK_APB>;
 295                                 no-loopback-test;
 296                                 status = "disabled";
 297                         };
 298
 299                         lpc: lpc@1e789000 {
 300                                 compatible = "aspeed,ast2500-lpc", "simple-mfd";
 301                                 reg = <0x1e789000 0x1000>;
 302
 303                                 #address-cells = <1>;
 304                                 #size-cells = <1>;
 305                                 ranges = <0x0 0x1e789000 0x1000>;
 306
 307                                 lpc_bmc: lpc-bmc@0 {
 308                                         compatible = "aspeed,ast2500-lpc-bmc";
 309                                         reg = <0x0 0x80>;
 310                                 };
 311
 312                                 lpc_host: lpc-host@80 {
 313                                         compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
 314                                         reg = <0x80 0x1e0>;
 315                                         reg-io-width = <4>;
 316
 317                                         #address-cells = <1>;
 318                                         #size-cells = <1>;
 319                                         ranges = <0x0 0x80 0x1e0>;
 320
 321                                         lpc_ctrl: lpc-ctrl@0 {
 322                                                 compatible = "aspeed,ast2500-lpc-ctrl";
 323                                                 reg = <0x0 0x80>;
 324                                                 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
 325                                                 status = "disabled";
 326                                         };
 327
 328                                         lpc_snoop: lpc-snoop@0 {
 329                                                 compatible = "aspeed,ast2500-lpc-snoop";
 330                                                 reg = <0x0 0x80>;
 331                                                 interrupts = <8>;
 332                                                 status = "disabled";
 333                                         };
 334
 335                                         lhc: lhc@20 {
 336                                                 compatible = "aspeed,ast2500-lhc";
 337                                                 reg = <0x20 0x24 0x48 0x8>;
 338                                         };
 339
 340                                         lpc_reset: reset-controller@18 {
 341                                                 compatible = "aspeed,ast2500-lpc-reset";
 342                                                 reg = <0x18 0x4>;
 343                                                 #reset-cells = <1>;
 344                                         };
 345
 346                                         ibt: ibt@c0 {
 347                                                 compatible = "aspeed,ast2500-ibt-bmc";
 348                                                 reg = <0xc0 0x18>;
 349                                                 interrupts = <8>;
 350                                                 status = "disabled";
 351                                         };
 352                                 };
 353                         };
 354
 355                         uart2: serial@1e78d000 {
 356                                 compatible = "ns16550a";
 357                                 reg = <0x1e78d000 0x20>;
 358                                 reg-shift = <2>;
 359                                 interrupts = <32>;
 360                                 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
 361                                 resets = <&lpc_reset 5>;
 362                                 no-loopback-test;
 363                                 status = "disabled";
 364                         };
 365
 366                         uart3: serial@1e78e000 {
 367                                 compatible = "ns16550a";
 368                                 reg = <0x1e78e000 0x20>;
 369                                 reg-shift = <2>;
 370                                 interrupts = <33>;
 371                                 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
 372                                 resets = <&lpc_reset 6>;
 373                                 no-loopback-test;
 374                                 status = "disabled";
 375                         };
 376
 377                         uart4: serial@1e78f000 {
 378                                 compatible = "ns16550a";
 379                                 reg = <0x1e78f000 0x20>;
 380                                 reg-shift = <2>;
 381                                 interrupts = <34>;
 382                                 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
 383                                 resets = <&lpc_reset 7>;
 384                                 no-loopback-test;
 385                                 status = "disabled";
 386                         };
 387
 388                         i2c: i2c@1e78a000 {
 389                                 compatible = "simple-bus";
 390                                 #address-cells = <1>;
 391                                 #size-cells = <1>;
 392                                 ranges = <0 0x1e78a000 0x1000>;
 393                         };
 394                 };
 395         };
 396 };
 397
 398 &i2c {
 399         i2c_ic: interrupt-controller@0 {
 400                 #interrupt-cells = <1>;
 401                 compatible = "aspeed,ast2500-i2c-ic";
 402                 reg = <0x0 0x40>;
 403                 interrupts = <12>;
 404                 interrupt-controller;
 405         };
 406
 407         i2c0: i2c-bus@40 {
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 #interrupt-cells = <1>;
 411
 412                 reg = <0x40 0x40>;
 413                 compatible = "aspeed,ast2500-i2c-bus";
 414                 clocks = <&syscon ASPEED_CLK_APB>;
 415                 resets = <&syscon ASPEED_RESET_I2C>;
 416                 bus-frequency = <100000>;
 417                 interrupts = <0>;
 418                 interrupt-parent = <&i2c_ic>;
 419                 status = "disabled";
 420                 /* Does not need pinctrl properties */
 421         };
 422
 423         i2c1: i2c-bus@80 {
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426                 #interrupt-cells = <1>;
 427
 428                 reg = <0x80 0x40>;
 429                 compatible = "aspeed,ast2500-i2c-bus";
 430                 clocks = <&syscon ASPEED_CLK_APB>;
 431                 resets = <&syscon ASPEED_RESET_I2C>;
 432                 bus-frequency = <100000>;
 433                 interrupts = <1>;
 434                 interrupt-parent = <&i2c_ic>;
 435                 status = "disabled";
 436                 /* Does not need pinctrl properties */
 437         };
 438
 439         i2c2: i2c-bus@c0 {
 440                 #address-cells = <1>;
 441                 #size-cells = <0>;
 442                 #interrupt-cells = <1>;
 443
 444                 reg = <0xc0 0x40>;
 445                 compatible = "aspeed,ast2500-i2c-bus";
 446                 clocks = <&syscon ASPEED_CLK_APB>;
 447                 resets = <&syscon ASPEED_RESET_I2C>;
 448                 bus-frequency = <100000>;
 449                 interrupts = <2>;
 450                 interrupt-parent = <&i2c_ic>;
 451                 pinctrl-names = "default";
 452                 pinctrl-0 = <&pinctrl_i2c3_default>;
 453                 status = "disabled";
 454         };
 455
 456         i2c3: i2c-bus@100 {
 457                 #address-cells = <1>;
 458                 #size-cells = <0>;
 459                 #interrupt-cells = <1>;
 460
 461                 reg = <0x100 0x40>;
 462                 compatible = "aspeed,ast2500-i2c-bus";
 463                 clocks = <&syscon ASPEED_CLK_APB>;
 464                 resets = <&syscon ASPEED_RESET_I2C>;
 465                 bus-frequency = <100000>;
 466                 interrupts = <3>;
 467                 interrupt-parent = <&i2c_ic>;
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&pinctrl_i2c4_default>;
 470                 status = "disabled";
 471         };
 472
 473         i2c4: i2c-bus@140 {
 474                 #address-cells = <1>;
 475                 #size-cells = <0>;
 476                 #interrupt-cells = <1>;
 477
 478                 reg = <0x140 0x40>;
 479                 compatible = "aspeed,ast2500-i2c-bus";
 480                 clocks = <&syscon ASPEED_CLK_APB>;
 481                 resets = <&syscon ASPEED_RESET_I2C>;
 482                 bus-frequency = <100000>;
 483                 interrupts = <4>;
 484                 interrupt-parent = <&i2c_ic>;
 485                 pinctrl-names = "default";
 486                 pinctrl-0 = <&pinctrl_i2c5_default>;
 487                 status = "disabled";
 488         };
 489
 490         i2c5: i2c-bus@180 {
 491                 #address-cells = <1>;
 492                 #size-cells = <0>;
 493                 #interrupt-cells = <1>;
 494
 495                 reg = <0x180 0x40>;
 496                 compatible = "aspeed,ast2500-i2c-bus";
 497                 clocks = <&syscon ASPEED_CLK_APB>;
 498                 resets = <&syscon ASPEED_RESET_I2C>;
 499                 bus-frequency = <100000>;
 500                 interrupts = <5>;
 501                 interrupt-parent = <&i2c_ic>;
 502                 pinctrl-names = "default";
 503                 pinctrl-0 = <&pinctrl_i2c6_default>;
 504                 status = "disabled";
 505         };
 506
 507         i2c6: i2c-bus@1c0 {
 508                 #address-cells = <1>;
 509                 #size-cells = <0>;
 510                 #interrupt-cells = <1>;
 511
 512                 reg = <0x1c0 0x40>;
 513                 compatible = "aspeed,ast2500-i2c-bus";
 514                 clocks = <&syscon ASPEED_CLK_APB>;
 515                 resets = <&syscon ASPEED_RESET_I2C>;
 516                 bus-frequency = <100000>;
 517                 interrupts = <6>;
 518                 interrupt-parent = <&i2c_ic>;
 519                 pinctrl-names = "default";
 520                 pinctrl-0 = <&pinctrl_i2c7_default>;
 521                 status = "disabled";
 522         };
 523
 524         i2c7: i2c-bus@300 {
 525                 #address-cells = <1>;
 526                 #size-cells = <0>;
 527                 #interrupt-cells = <1>;
 528
 529                 reg = <0x300 0x40>;
 530                 compatible = "aspeed,ast2500-i2c-bus";
 531                 clocks = <&syscon ASPEED_CLK_APB>;
 532                 resets = <&syscon ASPEED_RESET_I2C>;
 533                 bus-frequency = <100000>;
 534                 interrupts = <7>;
 535                 interrupt-parent = <&i2c_ic>;
 536                 pinctrl-names = "default";
 537                 pinctrl-0 = <&pinctrl_i2c8_default>;
 538                 status = "disabled";
 539         };
 540
 541         i2c8: i2c-bus@340 {
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 #interrupt-cells = <1>;
 545
 546                 reg = <0x340 0x40>;
 547                 compatible = "aspeed,ast2500-i2c-bus";
 548                 clocks = <&syscon ASPEED_CLK_APB>;
 549                 resets = <&syscon ASPEED_RESET_I2C>;
 550                 bus-frequency = <100000>;
 551                 interrupts = <8>;
 552                 interrupt-parent = <&i2c_ic>;
 553                 pinctrl-names = "default";
 554                 pinctrl-0 = <&pinctrl_i2c9_default>;
 555                 status = "disabled";
 556         };
 557
 558         i2c9: i2c-bus@380 {
 559                 #address-cells = <1>;
 560                 #size-cells = <0>;
 561                 #interrupt-cells = <1>;
 562
 563                 reg = <0x380 0x40>;
 564                 compatible = "aspeed,ast2500-i2c-bus";
 565                 clocks = <&syscon ASPEED_CLK_APB>;
 566                 resets = <&syscon ASPEED_RESET_I2C>;
 567                 bus-frequency = <100000>;
 568                 interrupts = <9>;
 569                 interrupt-parent = <&i2c_ic>;
 570                 pinctrl-names = "default";
 571                 pinctrl-0 = <&pinctrl_i2c10_default>;
 572                 status = "disabled";
 573         };
 574
 575         i2c10: i2c-bus@3c0 {
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 #interrupt-cells = <1>;
 579
 580                 reg = <0x3c0 0x40>;
 581                 compatible = "aspeed,ast2500-i2c-bus";
 582                 clocks = <&syscon ASPEED_CLK_APB>;
 583                 resets = <&syscon ASPEED_RESET_I2C>;
 584                 bus-frequency = <100000>;
 585                 interrupts = <10>;
 586                 interrupt-parent = <&i2c_ic>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&pinctrl_i2c11_default>;
 589                 status = "disabled";
 590         };
 591
 592         i2c11: i2c-bus@400 {
 593                 #address-cells = <1>;
 594                 #size-cells = <0>;
 595                 #interrupt-cells = <1>;
 596
 597                 reg = <0x400 0x40>;
 598                 compatible = "aspeed,ast2500-i2c-bus";
 599                 clocks = <&syscon ASPEED_CLK_APB>;
 600                 resets = <&syscon ASPEED_RESET_I2C>;
 601                 bus-frequency = <100000>;
 602                 interrupts = <11>;
 603                 interrupt-parent = <&i2c_ic>;
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&pinctrl_i2c12_default>;
 606                 status = "disabled";
 607         };
 608
 609         i2c12: i2c-bus@440 {
 610                 #address-cells = <1>;
 611                 #size-cells = <0>;
 612                 #interrupt-cells = <1>;
 613
 614                 reg = <0x440 0x40>;
 615                 compatible = "aspeed,ast2500-i2c-bus";
 616                 clocks = <&syscon ASPEED_CLK_APB>;
 617                 resets = <&syscon ASPEED_RESET_I2C>;
 618                 bus-frequency = <100000>;
 619                 interrupts = <12>;
 620                 interrupt-parent = <&i2c_ic>;
 621                 pinctrl-names = "default";
 622                 pinctrl-0 = <&pinctrl_i2c13_default>;
 623                 status = "disabled";
 624         };
 625
 626         i2c13: i2c-bus@480 {
 627                 #address-cells = <1>;
 628                 #size-cells = <0>;
 629                 #interrupt-cells = <1>;
 630
 631                 reg = <0x480 0x40>;
 632                 compatible = "aspeed,ast2500-i2c-bus";
 633                 clocks = <&syscon ASPEED_CLK_APB>;
 634                 resets = <&syscon ASPEED_RESET_I2C>;
 635                 bus-frequency = <100000>;
 636                 interrupts = <13>;
 637                 interrupt-parent = <&i2c_ic>;
 638                 pinctrl-names = "default";
 639                 pinctrl-0 = <&pinctrl_i2c14_default>;
 640                 status = "disabled";
 641         };
 642 };
 643
 644 &pinctrl {
 645         pinctrl_acpi_default: acpi_default {
 646                 function = "ACPI";
 647                 groups = "ACPI";
 648         };
 649
 650         pinctrl_adc0_default: adc0_default {
 651                 function = "ADC0";
 652                 groups = "ADC0";
 653         };
 654
 655         pinctrl_adc1_default: adc1_default {
 656                 function = "ADC1";
 657                 groups = "ADC1";
 658         };
 659
 660         pinctrl_adc10_default: adc10_default {
 661                 function = "ADC10";
 662                 groups = "ADC10";
 663         };
 664
 665         pinctrl_adc11_default: adc11_default {
 666                 function = "ADC11";
 667                 groups = "ADC11";
 668         };
 669
 670         pinctrl_adc12_default: adc12_default {
 671                 function = "ADC12";
 672                 groups = "ADC12";
 673         };
 674
 675         pinctrl_adc13_default: adc13_default {
 676                 function = "ADC13";
 677                 groups = "ADC13";
 678         };
 679
 680         pinctrl_adc14_default: adc14_default {
 681                 function = "ADC14";
 682                 groups = "ADC14";
 683         };
 684
 685         pinctrl_adc15_default: adc15_default {
 686                 function = "ADC15";
 687                 groups = "ADC15";
 688         };
 689
 690         pinctrl_adc2_default: adc2_default {
 691                 function = "ADC2";
 692                 groups = "ADC2";
 693         };
 694
 695         pinctrl_adc3_default: adc3_default {
 696                 function = "ADC3";
 697                 groups = "ADC3";
 698         };
 699
 700         pinctrl_adc4_default: adc4_default {
 701                 function = "ADC4";
 702                 groups = "ADC4";
 703         };
 704
 705         pinctrl_adc5_default: adc5_default {
 706                 function = "ADC5";
 707                 groups = "ADC5";
 708         };
 709
 710         pinctrl_adc6_default: adc6_default {
 711                 function = "ADC6";
 712                 groups = "ADC6";
 713         };
 714
 715         pinctrl_adc7_default: adc7_default {
 716                 function = "ADC7";
 717                 groups = "ADC7";
 718         };
 719
 720         pinctrl_adc8_default: adc8_default {
 721                 function = "ADC8";
 722                 groups = "ADC8";
 723         };
 724
 725         pinctrl_adc9_default: adc9_default {
 726                 function = "ADC9";
 727                 groups = "ADC9";
 728         };
 729
 730         pinctrl_bmcint_default: bmcint_default {
 731                 function = "BMCINT";
 732                 groups = "BMCINT";
 733         };
 734
 735         pinctrl_ddcclk_default: ddcclk_default {
 736                 function = "DDCCLK";
 737                 groups = "DDCCLK";
 738         };
 739
 740         pinctrl_ddcdat_default: ddcdat_default {
 741                 function = "DDCDAT";
 742                 groups = "DDCDAT";
 743         };
 744
 745         pinctrl_espi_default: espi_default {
 746                 function = "ESPI";
 747                 groups = "ESPI";
 748         };
 749
 750         pinctrl_fwspics1_default: fwspics1_default {
 751                 function = "FWSPICS1";
 752                 groups = "FWSPICS1";
 753         };
 754
 755         pinctrl_fwspics2_default: fwspics2_default {
 756                 function = "FWSPICS2";
 757                 groups = "FWSPICS2";
 758         };
 759
 760         pinctrl_gpid0_default: gpid0_default {
 761                 function = "GPID0";
 762                 groups = "GPID0";
 763         };
 764
 765         pinctrl_gpid2_default: gpid2_default {
 766                 function = "GPID2";
 767                 groups = "GPID2";
 768         };
 769
 770         pinctrl_gpid4_default: gpid4_default {
 771                 function = "GPID4";
 772                 groups = "GPID4";
 773         };
 774
 775         pinctrl_gpid6_default: gpid6_default {
 776                 function = "GPID6";
 777                 groups = "GPID6";
 778         };
 779
 780         pinctrl_gpie0_default: gpie0_default {
 781                 function = "GPIE0";
 782                 groups = "GPIE0";
 783         };
 784
 785         pinctrl_gpie2_default: gpie2_default {
 786                 function = "GPIE2";
 787                 groups = "GPIE2";
 788         };
 789
 790         pinctrl_gpie4_default: gpie4_default {
 791                 function = "GPIE4";
 792                 groups = "GPIE4";
 793         };
 794
 795         pinctrl_gpie6_default: gpie6_default {
 796                 function = "GPIE6";
 797                 groups = "GPIE6";
 798         };
 799
 800         pinctrl_i2c10_default: i2c10_default {
 801                 function = "I2C10";
 802                 groups = "I2C10";
 803         };
 804
 805         pinctrl_i2c11_default: i2c11_default {
 806                 function = "I2C11";
 807                 groups = "I2C11";
 808         };
 809
 810         pinctrl_i2c12_default: i2c12_default {
 811                 function = "I2C12";
 812                 groups = "I2C12";
 813         };
 814
 815         pinctrl_i2c13_default: i2c13_default {
 816                 function = "I2C13";
 817                 groups = "I2C13";
 818         };
 819
 820         pinctrl_i2c14_default: i2c14_default {
 821                 function = "I2C14";
 822                 groups = "I2C14";
 823         };
 824
 825         pinctrl_i2c3_default: i2c3_default {
 826                 function = "I2C3";
 827                 groups = "I2C3";
 828         };
 829
 830         pinctrl_i2c4_default: i2c4_default {
 831                 function = "I2C4";
 832                 groups = "I2C4";
 833         };
 834
 835         pinctrl_i2c5_default: i2c5_default {
 836                 function = "I2C5";
 837                 groups = "I2C5";
 838         };
 839
 840         pinctrl_i2c6_default: i2c6_default {
 841                 function = "I2C6";
 842                 groups = "I2C6";
 843         };
 844
 845         pinctrl_i2c7_default: i2c7_default {
 846                 function = "I2C7";
 847                 groups = "I2C7";
 848         };
 849
 850         pinctrl_i2c8_default: i2c8_default {
 851                 function = "I2C8";
 852                 groups = "I2C8";
 853         };
 854
 855         pinctrl_i2c9_default: i2c9_default {
 856                 function = "I2C9";
 857                 groups = "I2C9";
 858         };
 859
 860         pinctrl_lad0_default: lad0_default {
 861                 function = "LAD0";
 862                 groups = "LAD0";
 863         };
 864
 865         pinctrl_lad1_default: lad1_default {
 866                 function = "LAD1";
 867                 groups = "LAD1";
 868         };
 869
 870         pinctrl_lad2_default: lad2_default {
 871                 function = "LAD2";
 872                 groups = "LAD2";
 873         };
 874
 875         pinctrl_lad3_default: lad3_default {
 876                 function = "LAD3";
 877                 groups = "LAD3";
 878         };
 879
 880         pinctrl_lclk_default: lclk_default {
 881                 function = "LCLK";
 882                 groups = "LCLK";
 883         };
 884
 885         pinctrl_lframe_default: lframe_default {
 886                 function = "LFRAME";
 887                 groups = "LFRAME";
 888         };
 889
 890         pinctrl_lpchc_default: lpchc_default {
 891                 function = "LPCHC";
 892                 groups = "LPCHC";
 893         };
 894
 895         pinctrl_lpcpd_default: lpcpd_default {
 896                 function = "LPCPD";
 897                 groups = "LPCPD";
 898         };
 899
 900         pinctrl_lpcplus_default: lpcplus_default {
 901                 function = "LPCPLUS";
 902                 groups = "LPCPLUS";
 903         };
 904
 905         pinctrl_lpcpme_default: lpcpme_default {
 906                 function = "LPCPME";
 907                 groups = "LPCPME";
 908         };
 909
 910         pinctrl_lpcrst_default: lpcrst_default {
 911                 function = "LPCRST";
 912                 groups = "LPCRST";
 913         };
 914
 915         pinctrl_lpcsmi_default: lpcsmi_default {
 916                 function = "LPCSMI";
 917                 groups = "LPCSMI";
 918         };
 919
 920         pinctrl_lsirq_default: lsirq_default {
 921                 function = "LSIRQ";
 922                 groups = "LSIRQ";
 923         };
 924
 925         pinctrl_mac1link_default: mac1link_default {
 926                 function = "MAC1LINK";
 927                 groups = "MAC1LINK";
 928         };
 929
 930         pinctrl_mac2link_default: mac2link_default {
 931                 function = "MAC2LINK";
 932                 groups = "MAC2LINK";
 933         };
 934
 935         pinctrl_mdio1_default: mdio1_default {
 936                 function = "MDIO1";
 937                 groups = "MDIO1";
 938         };
 939
 940         pinctrl_mdio2_default: mdio2_default {
 941                 function = "MDIO2";
 942                 groups = "MDIO2";
 943         };
 944
 945         pinctrl_ncts1_default: ncts1_default {
 946                 function = "NCTS1";
 947                 groups = "NCTS1";
 948         };
 949
 950         pinctrl_ncts2_default: ncts2_default {
 951                 function = "NCTS2";
 952                 groups = "NCTS2";
 953         };
 954
 955         pinctrl_ncts3_default: ncts3_default {
 956                 function = "NCTS3";
 957                 groups = "NCTS3";
 958         };
 959
 960         pinctrl_ncts4_default: ncts4_default {
 961                 function = "NCTS4";
 962                 groups = "NCTS4";
 963         };
 964
 965         pinctrl_ndcd1_default: ndcd1_default {
 966                 function = "NDCD1";
 967                 groups = "NDCD1";
 968         };
 969
 970         pinctrl_ndcd2_default: ndcd2_default {
 971                 function = "NDCD2";
 972                 groups = "NDCD2";
 973         };
 974
 975         pinctrl_ndcd3_default: ndcd3_default {
 976                 function = "NDCD3";
 977                 groups = "NDCD3";
 978         };
 979
 980         pinctrl_ndcd4_default: ndcd4_default {
 981                 function = "NDCD4";
 982                 groups = "NDCD4";
 983         };
 984
 985         pinctrl_ndsr1_default: ndsr1_default {
 986                 function = "NDSR1";
 987                 groups = "NDSR1";
 988         };
 989
 990         pinctrl_ndsr2_default: ndsr2_default {
 991                 function = "NDSR2";
 992                 groups = "NDSR2";
 993         };
 994
 995         pinctrl_ndsr3_default: ndsr3_default {
 996                 function = "NDSR3";
 997                 groups = "NDSR3";
 998         };
 999
1000         pinctrl_ndsr4_default: ndsr4_default {
1001                 function = "NDSR4";
1002                 groups = "NDSR4";
1003         };
1004
1005         pinctrl_ndtr1_default: ndtr1_default {
1006                 function = "NDTR1";
1007                 groups = "NDTR1";
1008         };
1009
1010         pinctrl_ndtr2_default: ndtr2_default {
1011                 function = "NDTR2";
1012                 groups = "NDTR2";
1013         };
1014
1015         pinctrl_ndtr3_default: ndtr3_default {
1016                 function = "NDTR3";
1017                 groups = "NDTR3";
1018         };
1019
1020         pinctrl_ndtr4_default: ndtr4_default {
1021                 function = "NDTR4";
1022                 groups = "NDTR4";
1023         };
1024
1025         pinctrl_nri1_default: nri1_default {
1026                 function = "NRI1";
1027                 groups = "NRI1";
1028         };
1029
1030         pinctrl_nri2_default: nri2_default {
1031                 function = "NRI2";
1032                 groups = "NRI2";
1033         };
1034
1035         pinctrl_nri3_default: nri3_default {
1036                 function = "NRI3";
1037                 groups = "NRI3";
1038         };
1039
1040         pinctrl_nri4_default: nri4_default {
1041                 function = "NRI4";
1042                 groups = "NRI4";
1043         };
1044
1045         pinctrl_nrts1_default: nrts1_default {
1046                 function = "NRTS1";
1047                 groups = "NRTS1";
1048         };
1049
1050         pinctrl_nrts2_default: nrts2_default {
1051                 function = "NRTS2";
1052                 groups = "NRTS2";
1053         };
1054
1055         pinctrl_nrts3_default: nrts3_default {
1056                 function = "NRTS3";
1057                 groups = "NRTS3";
1058         };
1059
1060         pinctrl_nrts4_default: nrts4_default {
1061                 function = "NRTS4";
1062                 groups = "NRTS4";
1063         };
1064
1065         pinctrl_oscclk_default: oscclk_default {
1066                 function = "OSCCLK";
1067                 groups = "OSCCLK";
1068         };
1069
1070         pinctrl_pewake_default: pewake_default {
1071                 function = "PEWAKE";
1072                 groups = "PEWAKE";
1073         };
1074
1075         pinctrl_pnor_default: pnor_default {
1076                 function = "PNOR";
1077                 groups = "PNOR";
1078         };
1079
1080         pinctrl_pwm0_default: pwm0_default {
1081                 function = "PWM0";
1082                 groups = "PWM0";
1083         };
1084
1085         pinctrl_pwm1_default: pwm1_default {
1086                 function = "PWM1";
1087                 groups = "PWM1";
1088         };
1089
1090         pinctrl_pwm2_default: pwm2_default {
1091                 function = "PWM2";
1092                 groups = "PWM2";
1093         };
1094
1095         pinctrl_pwm3_default: pwm3_default {
1096                 function = "PWM3";
1097                 groups = "PWM3";
1098         };
1099
1100         pinctrl_pwm4_default: pwm4_default {
1101                 function = "PWM4";
1102                 groups = "PWM4";
1103         };
1104
1105         pinctrl_pwm5_default: pwm5_default {
1106                 function = "PWM5";
1107                 groups = "PWM5";
1108         };
1109
1110         pinctrl_pwm6_default: pwm6_default {
1111                 function = "PWM6";
1112                 groups = "PWM6";
1113         };
1114
1115         pinctrl_pwm7_default: pwm7_default {
1116                 function = "PWM7";
1117                 groups = "PWM7";
1118         };
1119
1120         pinctrl_rgmii1_default: rgmii1_default {
1121                 function = "RGMII1";
1122                 groups = "RGMII1";
1123         };
1124
1125         pinctrl_rgmii2_default: rgmii2_default {
1126                 function = "RGMII2";
1127                 groups = "RGMII2";
1128         };
1129
1130         pinctrl_rmii1_default: rmii1_default {
1131                 function = "RMII1";
1132                 groups = "RMII1";
1133         };
1134
1135         pinctrl_rmii2_default: rmii2_default {
1136                 function = "RMII2";
1137                 groups = "RMII2";
1138         };
1139
1140         pinctrl_rxd1_default: rxd1_default {
1141                 function = "RXD1";
1142                 groups = "RXD1";
1143         };
1144
1145         pinctrl_rxd2_default: rxd2_default {
1146                 function = "RXD2";
1147                 groups = "RXD2";
1148         };
1149
1150         pinctrl_rxd3_default: rxd3_default {
1151                 function = "RXD3";
1152                 groups = "RXD3";
1153         };
1154
1155         pinctrl_rxd4_default: rxd4_default {
1156                 function = "RXD4";
1157                 groups = "RXD4";
1158         };
1159
1160         pinctrl_salt1_default: salt1_default {
1161                 function = "SALT1";
1162                 groups = "SALT1";
1163         };
1164
1165         pinctrl_salt10_default: salt10_default {
1166                 function = "SALT10";
1167                 groups = "SALT10";
1168         };
1169
1170         pinctrl_salt11_default: salt11_default {
1171                 function = "SALT11";
1172                 groups = "SALT11";
1173         };
1174
1175         pinctrl_salt12_default: salt12_default {
1176                 function = "SALT12";
1177                 groups = "SALT12";
1178         };
1179
1180         pinctrl_salt13_default: salt13_default {
1181                 function = "SALT13";
1182                 groups = "SALT13";
1183         };
1184
1185         pinctrl_salt14_default: salt14_default {
1186                 function = "SALT14";
1187                 groups = "SALT14";
1188         };
1189
1190         pinctrl_salt2_default: salt2_default {
1191                 function = "SALT2";
1192                 groups = "SALT2";
1193         };
1194
1195         pinctrl_salt3_default: salt3_default {
1196                 function = "SALT3";
1197                 groups = "SALT3";
1198         };
1199
1200         pinctrl_salt4_default: salt4_default {
1201                 function = "SALT4";
1202                 groups = "SALT4";
1203         };
1204
1205         pinctrl_salt5_default: salt5_default {
1206                 function = "SALT5";
1207                 groups = "SALT5";
1208         };
1209
1210         pinctrl_salt6_default: salt6_default {
1211                 function = "SALT6";
1212                 groups = "SALT6";
1213         };
1214
1215         pinctrl_salt7_default: salt7_default {
1216                 function = "SALT7";
1217                 groups = "SALT7";
1218         };
1219
1220         pinctrl_salt8_default: salt8_default {
1221                 function = "SALT8";
1222                 groups = "SALT8";
1223         };
1224
1225         pinctrl_salt9_default: salt9_default {
1226                 function = "SALT9";
1227                 groups = "SALT9";
1228         };
1229
1230         pinctrl_scl1_default: scl1_default {
1231                 function = "SCL1";
1232                 groups = "SCL1";
1233         };
1234
1235         pinctrl_scl2_default: scl2_default {
1236                 function = "SCL2";
1237                 groups = "SCL2";
1238         };
1239
1240         pinctrl_sd1_default: sd1_default {
1241                 function = "SD1";
1242                 groups = "SD1";
1243         };
1244
1245         pinctrl_sd2_default: sd2_default {
1246                 function = "SD2";
1247                 groups = "SD2";
1248         };
1249
1250         pinctrl_sda1_default: sda1_default {
1251                 function = "SDA1";
1252                 groups = "SDA1";
1253         };
1254
1255         pinctrl_sda2_default: sda2_default {
1256                 function = "SDA2";
1257                 groups = "SDA2";
1258         };
1259
1260         pinctrl_sgps1_default: sgps1_default {
1261                 function = "SGPS1";
1262                 groups = "SGPS1";
1263         };
1264
1265         pinctrl_sgps2_default: sgps2_default {
1266                 function = "SGPS2";
1267                 groups = "SGPS2";
1268         };
1269
1270         pinctrl_sioonctrl_default: sioonctrl_default {
1271                 function = "SIOONCTRL";
1272                 groups = "SIOONCTRL";
1273         };
1274
1275         pinctrl_siopbi_default: siopbi_default {
1276                 function = "SIOPBI";
1277                 groups = "SIOPBI";
1278         };
1279
1280         pinctrl_siopbo_default: siopbo_default {
1281                 function = "SIOPBO";
1282                 groups = "SIOPBO";
1283         };
1284
1285         pinctrl_siopwreq_default: siopwreq_default {
1286                 function = "SIOPWREQ";
1287                 groups = "SIOPWREQ";
1288         };
1289
1290         pinctrl_siopwrgd_default: siopwrgd_default {
1291                 function = "SIOPWRGD";
1292                 groups = "SIOPWRGD";
1293         };
1294
1295         pinctrl_sios3_default: sios3_default {
1296                 function = "SIOS3";
1297                 groups = "SIOS3";
1298         };
1299
1300         pinctrl_sios5_default: sios5_default {
1301                 function = "SIOS5";
1302                 groups = "SIOS5";
1303         };
1304
1305         pinctrl_siosci_default: siosci_default {
1306                 function = "SIOSCI";
1307                 groups = "SIOSCI";
1308         };
1309
1310         pinctrl_spi1_default: spi1_default {
1311                 function = "SPI1";
1312                 groups = "SPI1";
1313         };
1314
1315         pinctrl_spi1cs1_default: spi1cs1_default {
1316                 function = "SPI1CS1";
1317                 groups = "SPI1CS1";
1318         };
1319
1320         pinctrl_spi1debug_default: spi1debug_default {
1321                 function = "SPI1DEBUG";
1322                 groups = "SPI1DEBUG";
1323         };
1324
1325         pinctrl_spi1passthru_default: spi1passthru_default {
1326                 function = "SPI1PASSTHRU";
1327                 groups = "SPI1PASSTHRU";
1328         };
1329
1330         pinctrl_spi2ck_default: spi2ck_default {
1331                 function = "SPI2CK";
1332                 groups = "SPI2CK";
1333         };
1334
1335         pinctrl_spi2cs0_default: spi2cs0_default {
1336                 function = "SPI2CS0";
1337                 groups = "SPI2CS0";
1338         };
1339
1340         pinctrl_spi2cs1_default: spi2cs1_default {
1341                 function = "SPI2CS1";
1342                 groups = "SPI2CS1";
1343         };
1344
1345         pinctrl_spi2miso_default: spi2miso_default {
1346                 function = "SPI2MISO";
1347                 groups = "SPI2MISO";
1348         };
1349
1350         pinctrl_spi2mosi_default: spi2mosi_default {
1351                 function = "SPI2MOSI";
1352                 groups = "SPI2MOSI";
1353         };
1354
1355         pinctrl_timer3_default: timer3_default {
1356                 function = "TIMER3";
1357                 groups = "TIMER3";
1358         };
1359
1360         pinctrl_timer4_default: timer4_default {
1361                 function = "TIMER4";
1362                 groups = "TIMER4";
1363         };
1364
1365         pinctrl_timer5_default: timer5_default {
1366                 function = "TIMER5";
1367                 groups = "TIMER5";
1368         };
1369
1370         pinctrl_timer6_default: timer6_default {
1371                 function = "TIMER6";
1372                 groups = "TIMER6";
1373         };
1374
1375         pinctrl_timer7_default: timer7_default {
1376                 function = "TIMER7";
1377                 groups = "TIMER7";
1378         };
1379
1380         pinctrl_timer8_default: timer8_default {
1381                 function = "TIMER8";
1382                 groups = "TIMER8";
1383         };
1384
1385         pinctrl_txd1_default: txd1_default {
1386                 function = "TXD1";
1387                 groups = "TXD1";
1388         };
1389
1390         pinctrl_txd2_default: txd2_default {
1391                 function = "TXD2";
1392                 groups = "TXD2";
1393         };
1394
1395         pinctrl_txd3_default: txd3_default {
1396                 function = "TXD3";
1397                 groups = "TXD3";
1398         };
1399
1400         pinctrl_txd4_default: txd4_default {
1401                 function = "TXD4";
1402                 groups = "TXD4";
1403         };
1404
1405         pinctrl_uart6_default: uart6_default {
1406                 function = "UART6";
1407                 groups = "UART6";
1408         };
1409
1410         pinctrl_usbcki_default: usbcki_default {
1411                 function = "USBCKI";
1412                 groups = "USBCKI";
1413         };
1414
1415         pinctrl_usb2ah_default: usb2ah_default {
1416                 function = "USB2AH";
1417                 groups = "USB2AH";
1418         };
1419
1420         pinctrl_usb11bhid_default: usb11bhid_default {
1421                 function = "USB11BHID";
1422                 groups = "USB11BHID";
1423         };
1424
1425         pinctrl_usb2bh_default: usb2bh_default {
1426                 function = "USB2BH";
1427                 groups = "USB2BH";
1428         };
1429
1430         pinctrl_vgabiosrom_default: vgabiosrom_default {
1431                 function = "VGABIOSROM";
1432                 groups = "VGABIOSROM";
1433         };
1434
1435         pinctrl_vgahs_default: vgahs_default {
1436                 function = "VGAHS";
1437                 groups = "VGAHS";
1438         };
1439
1440         pinctrl_vgavs_default: vgavs_default {
1441                 function = "VGAVS";
1442                 groups = "VGAVS";
1443         };
1444
1445         pinctrl_vpi24_default: vpi24_default {
1446                 function = "VPI24";
1447                 groups = "VPI24";
1448         };
1449
1450         pinctrl_vpo_default: vpo_default {
1451                 function = "VPO";
1452                 groups = "VPO";
1453         };
1454
1455         pinctrl_wdtrst1_default: wdtrst1_default {
1456                 function = "WDTRST1";
1457                 groups = "WDTRST1";
1458         };
1459
1460         pinctrl_wdtrst2_default: wdtrst2_default {
1461                 function = "WDTRST2";
1462                 groups = "WDTRST2";
1463         };
1464 };