arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3 #include "aspeed-g4.dtsi"
   4 #include <dt-bindings/gpio/aspeed-gpio.h>
   5
   6 / {
   7         model = "Quanta Q71L BMC";
   8         compatible = "quanta,q71l-bmc", "aspeed,ast2400";
   9
  10         aliases {
  11                 i2c14 = &i2c_pcie2;
  12                 i2c15 = &i2c_pcie3;
  13                 i2c16 = &i2c_pcie6;
  14                 i2c17 = &i2c_pcie7;
  15                 i2c18 = &i2c_pcie1;
  16                 i2c19 = &i2c_pcie4;
  17                 i2c20 = &i2c_pcie5;
  18                 i2c21 = &i2c_pcie8;
  19                 i2c22 = &i2c_pcie9;
  20                 i2c23 = &i2c_pcie10;
  21                 i2c24 = &i2c_ssd1;
  22                 i2c25 = &i2c_ssd2;
  23                 i2c26 = &i2c_psu4;
  24                 i2c27 = &i2c_psu1;
  25                 i2c28 = &i2c_psu3;
  26                 i2c29 = &i2c_psu2;
  27         };
  28
  29         chosen {
  30                 stdout-path = &uart5;
  31                 bootargs = "console=ttyS4,115200 earlyprintk";
  32         };
  33
  34         memory@40000000 {
  35                 reg = <0x40000000 0x8000000>;
  36         };
  37
  38         reserved-memory {
  39                 #address-cells = <1>;
  40                 #size-cells = <1>;
  41                 ranges;
  42
  43                 vga_memory: framebuffer@47800000 {
  44                         no-map;
  45                         reg = <0x47800000 0x00800000>; /* 8MB */
  46                 };
  47         };
  48
  49         leds {
  50                 compatible = "gpio-leds";
  51
  52                 heartbeat {
  53                         gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
  54                 };
  55
  56                 power {
  57                         gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
  58                 };
  59
  60                 identify {
  61                         gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
  62                 };
  63         };
  64
  65         iio-hwmon {
  66                 compatible = "iio-hwmon";
  67                 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
  68                         <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
  69                         <&adc 8>, <&adc 9>, <&adc 10>;
  70         };
  71
  72         iio-hwmon-battery {
  73                 compatible = "iio-hwmon";
  74                 io-channels = <&adc 11>;
  75         };
  76
  77         i2c1mux: i2cmux {
  78                 compatible = "i2c-mux-gpio";
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 /* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */
  83                 i2c-parent = <&i2c1>;
  84         };
  85 };
  86
  87 &fmc {
  88         status = "okay";
  89         flash@0 {
  90                 status = "okay";
  91                 label = "bmc";
  92                 m25p,fast-read;
  93 #include "openbmc-flash-layout.dtsi"
  94         };
  95 };
  96
  97 &spi {
  98         status = "okay";
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&pinctrl_spi1_default>;
 101
 102         flash@0 {
 103                 status = "okay";
 104                 m25p,fast-read;
 105                 label = "pnor";
 106         };
 107 };
 108
 109 &pinctrl {
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default
 112                         &pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
 113 };
 114
 115 &ibt {
 116         status = "okay";
 117 };
 118
 119 &lpc_snoop {
 120         status = "okay";
 121         snoop-ports = <0x80>;
 122 };
 123
 124 &mac0 {
 125         status = "okay";
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&pinctrl_rmii1_default>;
 128         use-ncsi;
 129 };
 130
 131 &mac1 {
 132         status = "okay";
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
 135 };
 136
 137 &uart5 {
 138         status = "okay";
 139 };
 140
 141 &i2c0 {
 142         status = "okay";
 143 };
 144
 145 &i2c1 {
 146         status = "okay";
 147
 148         /* temp2 inlet */
 149         tmp75@4c {
 150                 compatible = "ti,tmp75";
 151                 reg = <0x4c>;
 152         };
 153
 154         /* temp3 */
 155         tmp75@4e {
 156                 compatible = "ti,tmp75";
 157                 reg = <0x4e>;
 158         };
 159
 160         /* temp1 */
 161         tmp75@4f {
 162                 compatible = "ti,tmp75";
 163                 reg = <0x4f>;
 164         };
 165
 166         /* Baseboard FRU */
 167         eeprom@54 {
 168                 compatible = "atmel,24c64";
 169                 reg = <0x54>;
 170         };
 171
 172         /* FP FRU */
 173         eeprom@57 {
 174                 compatible = "atmel,24c64";
 175                 reg = <0x57>;
 176         };
 177 };
 178
 179 &i2c2 {
 180         status = "okay";
 181
 182         /* 0: PCIe Slot 2,
 183          *    Slot 3,
 184          *    Slot 6,
 185          *    Slot 7
 186          */
 187         i2c-switch@74 {
 188                 compatible = "nxp,pca9546";
 189                 reg = <0x74>;
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192                 i2c-mux-idle-disconnect;  /* may use mux@77 next. */
 193
 194                 i2c_pcie2: i2c@0 {
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         reg = <0>;
 198                 };
 199
 200                 i2c_pcie3: i2c@1 {
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         reg = <1>;
 204                 };
 205
 206                 i2c_pcie6: i2c@2 {
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         reg = <2>;
 210                 };
 211
 212                 i2c_pcie7: i2c@3 {
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215                         reg = <3>;
 216                 };
 217         };
 218
 219         /* 0: PCIe Slot 1,
 220          *    Slot 4,
 221          *    Slot 5,
 222          *    Slot 8,
 223          *    Slot 9,
 224          *    Slot 10,
 225          *    SSD 1,
 226          *    SSD 2
 227          */
 228         i2c-switch@77 {
 229                 compatible = "nxp,pca9548";
 230                 #address-cells = <1>;
 231                 #size-cells = <0>;
 232                 reg = <0x77>;
 233                 i2c-mux-idle-disconnect;  /* may use mux@74 next. */
 234
 235                 i2c_pcie1: i2c@0 {
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238                         reg = <0>;
 239                 };
 240
 241                 i2c_pcie4: i2c@1 {
 242                         #address-cells = <1>;
 243                         #size-cells = <0>;
 244                         reg = <1>;
 245                 };
 246
 247                 i2c_pcie5: i2c@2 {
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                         reg = <2>;
 251                 };
 252
 253                 i2c_pcie8: i2c@3 {
 254                         #address-cells = <1>;
 255                         #size-cells = <0>;
 256                         reg = <3>;
 257                 };
 258
 259                 i2c_pcie9: i2c@4 {
 260                         #address-cells = <1>;
 261                         #size-cells = <0>;
 262                         reg = <4>;
 263                 };
 264
 265                 i2c_pcie10: i2c@5 {
 266                         #address-cells = <1>;
 267                         #size-cells = <0>;
 268                         reg = <5>;
 269                 };
 270
 271                 i2c_ssd1: i2c@6 {
 272                         #address-cells = <1>;
 273                         #size-cells = <0>;
 274                         reg = <6>;
 275                 };
 276
 277                 i2c_ssd2: i2c@7 {
 278                         #address-cells = <1>;
 279                         #size-cells = <0>;
 280                         reg = <7>;
 281                 };
 282         };
 283 };
 284
 285 &i2c3 {
 286         status = "okay";
 287
 288         /* BIOS FRU */
 289         eeprom@56 {
 290                 compatible = "atmel,24c64";
 291                 reg = <0x56>;
 292         };
 293 };
 294
 295 &i2c4 {
 296         status = "okay";
 297 };
 298
 299 &i2c5 {
 300         status = "okay";
 301 };
 302
 303 &i2c6 {
 304         status = "okay";
 305 };
 306
 307 &i2c7 {
 308         status = "okay";
 309
 310         /* 0: PSU4
 311          *    PSU1
 312          *    PSU3
 313          *    PSU2
 314          */
 315         i2c-switch@70 {
 316                 compatible = "nxp,pca9546";
 317                 reg = <0x70>;
 318                 #address-cells = <1>;
 319                 #size-cells = <0>;
 320
 321                 i2c_psu4: i2c@0 {
 322                         #address-cells = <1>;
 323                         #size-cells = <0>;
 324                         reg = <0>;
 325
 326                         psu@59 {
 327                                 compatible = "pmbus";
 328                                 reg = <0x59>;
 329                         };
 330                 };
 331
 332                 i2c_psu1: i2c@1 {
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         reg = <1>;
 336
 337                         psu@58 {
 338                                 compatible = "pmbus";
 339                                 reg = <0x58>;
 340                         };
 341                 };
 342
 343                 i2c_psu3: i2c@2 {
 344                         #address-cells = <1>;
 345                         #size-cells = <0>;
 346                         reg = <2>;
 347
 348                         psu@58 {
 349                                 compatible = "pmbus";
 350                                 reg = <0x58>;
 351                         };
 352                 };
 353
 354                 i2c_psu2: i2c@3 {
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         reg = <3>;
 358
 359                         psu@59 {
 360                                 compatible = "pmbus";
 361                                 reg = <0x59>;
 362                         };
 363                 };
 364         };
 365
 366         /* PDB FRU */
 367         eeprom@52 {
 368                 compatible = "atmel,24c64";
 369                 reg = <0x52>;
 370         };
 371 };
 372
 373 &i2c8 {
 374         status = "okay";
 375
 376         /* BMC FRU */
 377         eeprom@50 {
 378                 compatible = "atmel,24c64";
 379                 reg = <0x50>;
 380         };
 381 };
 382
 383 &vuart {
 384         status = "okay";
 385 };
 386
 387 &wdt2 {
 388         status = "okay";
 389 };
 390
 391 &adc {
 392         status = "okay";
 393 };
 394
 395 &pwm_tacho {
 396         status = "okay";
 397
 398         pinctrl-names = "default";
 399         pinctrl-0 = <&pinctrl_pwm0_default
 400                 &pinctrl_pwm1_default
 401                 &pinctrl_pwm2_default
 402                 &pinctrl_pwm3_default>;
 403
 404         fan@0 {
 405                 reg = <0x00>;
 406                 aspeed,fan-tach-ch = /bits/ 8 <0x00>;
 407         };
 408
 409         fan@1 {
 410                 reg = <0x01>;
 411                 aspeed,fan-tach-ch = /bits/ 8 <0x01>;
 412         };
 413
 414         fan@2 {
 415                 reg = <0x02>;
 416                 aspeed,fan-tach-ch = /bits/ 8 <0x02>;
 417         };
 418
 419         fan@3 {
 420                 reg = <0x03>;
 421                 aspeed,fan-tach-ch = /bits/ 8 <0x03>;
 422         };
 423
 424         fan@4 {
 425                 reg = <0x00>;
 426                 aspeed,fan-tach-ch = /bits/ 8 <0x04>;
 427         };
 428
 429         fan@5 {
 430                 reg = <0x01>;
 431                 aspeed,fan-tach-ch = /bits/ 8 <0x05>;
 432         };
 433
 434         fan@6 {
 435                 reg = <0x02>;
 436                 aspeed,fan-tach-ch = /bits/ 8 <0x06>;
 437         };
 438
 439         fan@7 {
 440                 reg = <0x03>;
 441                 aspeed,fan-tach-ch = /bits/ 8 <0x07>;
 442         };
 443 };
 444
 445 &i2c1mux {
 446         i2c@0 {
 447                 reg = <0>;
 448                 #address-cells = <1>;
 449                 #size-cells = <0>;
 450
 451                 /* Memory Riser 1 FRU */
 452                 eeprom@50 {
 453                         compatible = "atmel,24c02";
 454                         reg = <0x50>;
 455                 };
 456
 457                 /* Memory Riser 2 FRU */
 458                 eeprom@51 {
 459                         compatible = "atmel,24c02";
 460                         reg = <0x51>;
 461                 };
 462
 463                 /* Memory Riser 3 FRU */
 464                 eeprom@52 {
 465                         compatible = "atmel,24c02";
 466                         reg = <0x52>;
 467                 };
 468
 469                 /* Memory Riser 4 FRU */
 470                 eeprom@53 {
 471                         compatible = "atmel,24c02";
 472                         reg = <0x53>;
 473                 };
 474         };
 475
 476         i2c@1 {
 477                 reg = <1>;
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480
 481                 /* Memory Riser 5 FRU */
 482                 eeprom@50 {
 483                         compatible = "atmel,24c02";
 484                         reg = <0x50>;
 485                 };
 486
 487                 /* Memory Riser 6 FRU */
 488                 eeprom@51 {
 489                         compatible = "atmel,24c02";
 490                         reg = <0x51>;
 491                 };
 492
 493                 /* Memory Riser 7 FRU */
 494                 eeprom@52 {
 495                         compatible = "atmel,24c02";
 496                         reg = <0x52>;
 497                 };
 498
 499                 /* Memory Riser 8 FRU */
 500                 eeprom@53 {
 501                         compatible = "atmel,24c02";
 502                         reg = <0x53>;
 503                 };
 504         };
 505 };