arch/arm/boot/dts/armada-388-clearfog.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Device Tree include file for SolidRun Clearfog 88F6828 based boards
   4  *
   5  *  Copyright (C) 2015 Russell King
   6  *
   7  * This board is in development; the contents of this file work with
   8  * the A1 rev 2.0 of the board, which does not represent final
   9  * production board.  Things will change, don't expect this file to
  10  * remain compatible info the future.
  11  */
  12
  13 #include "armada-388.dtsi"
  14 #include "armada-38x-solidrun-microsom.dtsi"
  15
  16 / {
  17         aliases {
  18                 /* So that mvebu u-boot can update the MAC addresses */
  19                 ethernet1 = &eth0;
  20                 ethernet2 = &eth1;
  21                 ethernet3 = &eth2;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26         };
  27
  28         reg_3p3v: regulator-3p3v {
  29                 compatible = "regulator-fixed";
  30                 regulator-name = "3P3V";
  31                 regulator-min-microvolt = <3300000>;
  32                 regulator-max-microvolt = <3300000>;
  33                 regulator-always-on;
  34         };
  35
  36         soc {
  37                 internal-regs {
  38                         sata@a8000 {
  39                                 /* pinctrl? */
  40                                 status = "okay";
  41                         };
  42
  43                         sata@e0000 {
  44                                 /* pinctrl? */
  45                                 status = "okay";
  46                         };
  47
  48                         sdhci@d8000 {
  49                                 bus-width = <4>;
  50                                 cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
  51                                 no-1-8-v;
  52                                 pinctrl-0 = <&microsom_sdhci_pins
  53                                              &clearfog_sdhci_cd_pins>;
  54                                 pinctrl-names = "default";
  55                                 status = "okay";
  56                                 vmmc = <&reg_3p3v>;
  57                                 wp-inverted;
  58                         };
  59
  60                         usb@58000 {
  61                                 /* CON3, nearest  power. */
  62                                 status = "okay";
  63                         };
  64
  65                         usb3@f8000 {
  66                                 /* CON7 */
  67                                 status = "okay";
  68                         };
  69                 };
  70
  71                 pcie {
  72                         status = "okay";
  73                         /*
  74                          * The two PCIe units are accessible through
  75                          * the mini-PCIe connectors on the board.
  76                          */
  77                         pcie@2,0 {
  78                                 /* Port 1, Lane 0. CON3, nearest power. */
  79                                 reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
  80                                 status = "okay";
  81                         };
  82                 };
  83         };
  84
  85         sfp: sfp {
  86                 compatible = "sff,sfp";
  87                 i2c-bus = <&i2c1>;
  88                 los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
  89                 mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
  90                 tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
  91                 tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
  92                 maximum-power-milliwatt = <2000>;
  93         };
  94 };
  95
  96 &eth1 {
  97         /* ethernet@30000 */
  98         bm,pool-long = <2>;
  99         bm,pool-short = <1>;
 100         buffer-manager = <&bm>;
 101         phy-mode = "sgmii";
 102         status = "okay";
 103 };
 104
 105 &eth2 {
 106         /* ethernet@34000 */
 107         bm,pool-long = <3>;
 108         bm,pool-short = <1>;
 109         buffer-manager = <&bm>;
 110         managed = "in-band-status";
 111         phy-mode = "sgmii";
 112         sfp = <&sfp>;
 113         status = "okay";
 114 };
 115
 116 &i2c0 {
 117         clock-frequency = <400000>;
 118         pinctrl-0 = <&i2c0_pins>;
 119         pinctrl-names = "default";
 120         status = "okay";
 121
 122         /*
 123          * PCA9655 GPIO expander, up to 1MHz clock.
 124          *  0-CON3 CLKREQ#
 125          *  1-CON3 PERST#
 126          *  2-
 127          *  3-CON3 W_DISABLE
 128          *  4-
 129          *  5-USB3 overcurrent
 130          *  6-USB3 power
 131          *  7-
 132          *  8-JP4 P1
 133          *  9-JP4 P4
 134          * 10-JP4 P5
 135          * 11-m.2 DEVSLP
 136          * 12-SFP_LOS
 137          * 13-SFP_TX_FAULT
 138          * 14-SFP_TX_DISABLE
 139          * 15-SFP_MOD_DEF0
 140          */
 141         expander0: gpio-expander@20 {
 142                 /*
 143                  * This is how it should be:
 144                  * compatible = "onnn,pca9655", "nxp,pca9555";
 145                  * but you can't do this because of the way I2C works.
 146                  */
 147                 compatible = "nxp,pca9555";
 148                 gpio-controller;
 149                 #gpio-cells = <2>;
 150                 reg = <0x20>;
 151
 152                 pcie1_0_clkreq {
 153                         gpio-hog;
 154                         gpios = <0 GPIO_ACTIVE_LOW>;
 155                         input;
 156                         line-name = "pcie1.0-clkreq";
 157                 };
 158                 pcie1_0_w_disable {
 159                         gpio-hog;
 160                         gpios = <3 GPIO_ACTIVE_LOW>;
 161                         output-low;
 162                         line-name = "pcie1.0-w-disable";
 163                 };
 164                 usb3_ilimit {
 165                         gpio-hog;
 166                         gpios = <5 GPIO_ACTIVE_LOW>;
 167                         input;
 168                         line-name = "usb3-current-limit";
 169                 };
 170                 usb3_power {
 171                         gpio-hog;
 172                         gpios = <6 GPIO_ACTIVE_HIGH>;
 173                         output-high;
 174                         line-name = "usb3-power";
 175                 };
 176                 m2_devslp {
 177                         gpio-hog;
 178                         gpios = <11 GPIO_ACTIVE_HIGH>;
 179                         output-low;
 180                         line-name = "m.2 devslp";
 181                 };
 182         };
 183
 184         /* The MCP3021 supports standard and fast modes */
 185         mikrobus_adc: mcp3021@4c {
 186                 compatible = "microchip,mcp3021";
 187                 reg = <0x4c>;
 188         };
 189 };
 190
 191 &i2c1 {
 192         /*
 193          * Routed to SFP, mikrobus, and PCIe.
 194          * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
 195          *  address pins tied low, which takes addresses 0x50 and 0x51.
 196          * Mikrobus doesn't specify beyond an I2C bus being present.
 197          * PCIe uses ARP to assign addresses, or 0x63-0x64.
 198          */
 199         clock-frequency = <100000>;
 200         pinctrl-0 = <&clearfog_i2c1_pins>;
 201         pinctrl-names = "default";
 202         status = "okay";
 203 };
 204
 205 &pinctrl {
 206         clearfog_i2c1_pins: i2c1-pins {
 207                 /* SFP, PCIe, mSATA, mikrobus */
 208                 marvell,pins = "mpp26", "mpp27";
 209                 marvell,function = "i2c1";
 210         };
 211         clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
 212                 marvell,pins = "mpp20";
 213                 marvell,function = "gpio";
 214         };
 215         mikro_pins: mikro-pins {
 216                 /* int: mpp22 rst: mpp29 */
 217                 marvell,pins = "mpp22", "mpp29";
 218                 marvell,function = "gpio";
 219         };
 220         mikro_spi_pins: mikro-spi-pins {
 221                 marvell,pins = "mpp43";
 222                 marvell,function = "spi1";
 223         };
 224         mikro_uart_pins: mikro-uart-pins {
 225                 marvell,pins = "mpp24", "mpp25";
 226                 marvell,function = "ua1";
 227         };
 228 };
 229
 230 &spi1 {
 231         /*
 232          * Add SPI CS pins for clearfog:
 233          * CS0: W25Q32 (not populated on uSOM)
 234          * CS1: PIC microcontroller (Pro models)
 235          * CS2: mikrobus
 236          */
 237         pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
 238         pinctrl-names = "default";
 239         status = "okay";
 240 };
 241
 242 &uart1 {
 243         /* mikrobus uart */
 244         pinctrl-0 = <&mikro_uart_pins>;
 245         pinctrl-names = "default";
 246         status = "okay";
 247 };