2 * Copyright (C) 2015 Phytec Messtechnik GmbH
3 * Author: Teresa Remmet <t.remmet@phytec.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include "am33xx.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
14 model = "Phytec AM335x phyCORE";
15 compatible = "phytec,am335x-phycore-som", "ti,am33xx";
24 cpu0-supply = <&vdd1_reg>;
29 device_type = "memory";
30 reg = <0x80000000 0x10000000>; /* 256 MB */
34 compatible = "simple-bus";
36 vcc5v: fixedregulator0 {
37 compatible = "regulator-fixed";
38 regulator-name = "vcc5v";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
58 ethernet0_pins: pinmux_ethernet0 {
59 pinctrl-single,pins = <
60 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
61 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)
62 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1)
63 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1)
64 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1)
65 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)
66 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)
67 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
71 mdio_pins: pinmux_mdio {
72 pinctrl-single,pins = <
74 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
75 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
83 dual_emac_res_vlan = <1>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&mdio_pins>;
91 phy0: ethernet-phy@0 {
98 pinctrl-names = "default";
99 pinctrl-0 = <ðernet0_pins>;
105 i2c0_pins: pinmux_i2c0 {
106 pinctrl-single,pins = <
107 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
108 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
114 pinctrl-names = "default";
115 pinctrl-0 = <&i2c0_pins>;
116 clock-frequency = <400000>;
123 i2c_tmp102: temp@4b {
124 compatible = "ti,tmp102";
129 i2c_eeprom: eeprom@52 {
130 compatible = "atmel,24c32";
137 compatible = "microcrystal,rv4162";
145 nandflash_pins: pinmux_nandflash {
146 pinctrl-single,pins = <
147 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
148 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
149 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
150 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
151 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
152 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
153 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
154 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
155 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
156 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
157 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
158 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
159 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
160 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
171 pinctrl-names = "default";
172 pinctrl-0 = <&nandflash_pins>;
173 ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
174 nandflash: nand@0,0 {
175 compatible = "ti,omap2-nand";
176 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
177 interrupt-parent = <&gpmc>;
178 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
179 <1 IRQ_TYPE_NONE>; /* termcount */
180 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
181 nand-bus-width = <8>;
182 ti,nand-ecc-opt = "bch8";
183 gpmc,device-nand = "true";
184 gpmc,device-width = <1>;
185 gpmc,sync-clk-ps = <0>;
187 gpmc,cs-rd-off-ns = <30>;
188 gpmc,cs-wr-off-ns = <30>;
189 gpmc,adv-on-ns = <0>;
190 gpmc,adv-rd-off-ns = <30>;
191 gpmc,adv-wr-off-ns = <30>;
193 gpmc,we-off-ns = <20>;
194 gpmc,oe-on-ns = <10>;
195 gpmc,oe-off-ns = <30>;
196 gpmc,access-ns = <30>;
197 gpmc,rd-cycle-ns = <30>;
198 gpmc,wr-cycle-ns = <30>;
199 gpmc,bus-turnaround-ns = <0>;
200 gpmc,cycle2cycle-delay-ns = <50>;
201 gpmc,cycle2cycle-diffcsen;
202 gpmc,clk-activation-ns = <0>;
203 gpmc,wr-access-ns = <30>;
204 gpmc,wr-data-mux-bus-ns = <0>;
208 #address-cells = <1>;
214 #include "tps65910.dtsi"
217 vcc1-supply = <&vcc5v>;
218 vcc2-supply = <&vcc5v>;
219 vcc3-supply = <&vcc5v>;
220 vcc4-supply = <&vcc5v>;
221 vcc5-supply = <&vcc5v>;
222 vcc6-supply = <&vcc5v>;
223 vcc7-supply = <&vcc5v>;
224 vccio-supply = <&vcc5v>;
227 vrtc_reg: regulator@0 {
231 vio_reg: regulator@1 {
235 vdd1_reg: regulator@2 {
236 /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
237 regulator-name = "vdd_mpu";
238 regulator-min-microvolt = <912500>;
239 regulator-max-microvolt = <1378000>;
244 vdd2_reg: regulator@3 {
245 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
246 regulator-name = "vdd_core";
247 regulator-min-microvolt = <912500>;
248 regulator-max-microvolt = <1150000>;
253 vdd3_reg: regulator@4 {
257 vdig1_reg: regulator@5 {
258 regulator-name = "vdig1_1p8v";
259 regulator-min-microvolt = <1800000>;
260 regulator-max-microvolt = <1800000>;
263 vdig2_reg: regulator@6 {
267 vpll_reg: regulator@7 {
271 vdac_reg: regulator@8 {
275 vaux1_reg: regulator@9 {
279 vaux2_reg: regulator@10 {
283 vaux33_reg: regulator@11 {
287 vmmc_reg: regulator@12 {
288 regulator-min-microvolt = <3300000>;
289 regulator-max-microvolt = <3300000>;
297 spi0_pins: pinmux_spi0 {
298 pinctrl-single,pins = <
299 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
300 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)
301 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
302 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
308 pinctrl-names = "default";
309 pinctrl-0 = <&spi0_pins>;
312 serial_flash: m25p80@0 {
313 compatible = "jedec,spi-nor";
314 spi-max-frequency = <48000000>;
318 #address-cells = <1>;