2 * Copyright(c) 2015 EZchip Technologies.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
17 #ifndef _PLAT_EZNPS_CTOP_H
18 #define _PLAT_EZNPS_CTOP_H
20 #ifndef CONFIG_ARC_PLAT_EZNPS
21 #error "Incorrect ctop.h include"
24 #include <linux/types.h>
25 #include <soc/nps/common.h>
27 /* core auxiliary registers */
29 #define CTOP_AUX_BASE (-0x800)
31 #define CTOP_AUX_BASE 0xFFFFF800
34 #define CTOP_AUX_GLOBAL_ID (CTOP_AUX_BASE + 0x000)
35 #define CTOP_AUX_CLUSTER_ID (CTOP_AUX_BASE + 0x004)
36 #define CTOP_AUX_CORE_ID (CTOP_AUX_BASE + 0x008)
37 #define CTOP_AUX_THREAD_ID (CTOP_AUX_BASE + 0x00C)
38 #define CTOP_AUX_LOGIC_GLOBAL_ID (CTOP_AUX_BASE + 0x010)
39 #define CTOP_AUX_LOGIC_CLUSTER_ID (CTOP_AUX_BASE + 0x014)
40 #define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018)
41 #define CTOP_AUX_MT_CTRL (CTOP_AUX_BASE + 0x020)
42 #define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024)
43 #define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C)
44 #define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030)
45 #define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080)
46 #define CTOP_AUX_IACK (CTOP_AUX_BASE + 0x088)
47 #define CTOP_AUX_GPA1 (CTOP_AUX_BASE + 0x08C)
48 #define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)
50 /* EZchip core instructions */
51 #define CTOP_INST_HWSCHD_WFT_IE12 0x3E6F7344
52 #define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF
53 #define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103
54 #define CTOP_INST_SCHD_RW 0x3E6F7004
55 #define CTOP_INST_SCHD_RD 0x3E6F7084
56 #define CTOP_INST_ASRI_0_R3 0x3B56003E
57 #define CTOP_INST_XEX_DI_R2_R2_R3 0x4A664C00
58 #define CTOP_INST_EXC_DI_R2_R2_R3 0x4A664C01
59 #define CTOP_INST_AADD_DI_R2_R2_R3 0x4A664C02
60 #define CTOP_INST_AAND_DI_R2_R2_R3 0x4A664C04
61 #define CTOP_INST_AOR_DI_R2_R2_R3 0x4A664C05
62 #define CTOP_INST_AXOR_DI_R2_R2_R3 0x4A664C06
64 /* Do not use D$ for address in 2G-3G */
65 #define HW_COMPLY_KRN_NOT_D_CACHED _BITUL(28)
67 #define NPS_MSU_EN_CFG 0x80
68 #define NPS_CRG_BLKID 0x480
69 #define NPS_CRG_SYNC_BIT _BITUL(0)
70 #define NPS_GIM_BLKID 0x5C0
72 /* GIM registers and fields*/
73 #define NPS_GIM_UART_LINE _BITUL(7)
74 #define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE _BITUL(10)
75 #define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE _BITUL(11)
76 #define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE _BITUL(25)
77 #define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE _BITUL(26)
80 /* Functional registers definition */
81 struct nps_host_reg_mtm_cfg {
84 u32 gen:1, gdis:1, clk_gate_dis:1, asb:1,
85 __reserved:9, nat:3, ten:16;
91 struct nps_host_reg_mtm_cpu_cfg {
94 u32 csa:22, dmsid:6, __reserved:3, cs:1;
100 struct nps_host_reg_thr_init {
103 u32 str:1, __reserved:27, thr_id:4;
109 struct nps_host_reg_thr_init_sts {
112 u32 bsy:1, err:1, __reserved:26, thr_id:4;
118 struct nps_host_reg_msu_en_cfg {
122 rtc_en:1, ipc_en:1, gim_1_en:1,
123 gim_0_en:1, ipi_en:1, buff_e_rls_bmuw:1,
124 buff_e_alc_bmuw:1, buff_i_rls_bmuw:1, buff_i_alc_bmuw:1,
125 buff_e_rls_bmue:1, buff_e_alc_bmue:1, buff_i_rls_bmue:1,
126 buff_i_alc_bmue:1, __reserved2:1, buff_e_pre_en:1,
127 buff_i_pre_en:1, pmuw_ja_en:1, pmue_ja_en:1,
128 pmuw_nj_en:1, pmue_nj_en:1, msu_en:1;
134 struct nps_host_reg_gim_p_int_dst {
137 u32 int_out_en:1, __reserved1:4,
138 is:1, intm:2, __reserved2:4,
139 nid:4, __reserved3:4, cid:4,
140 __reserved4:4, tid:4;
146 /* AUX registers definition */
147 struct nps_host_reg_aux_dpc {
150 u32 ien:1, men:1, hen:1, reserved:29;
156 struct nps_host_reg_aux_udmc {
159 u32 dcp:1, cme:1, __reserved:19, nat:3,
160 __reserved2:5, dcas:3;
166 struct nps_host_reg_aux_mt_ctrl {
169 u32 mten:1, hsen:1, scd:1, sten:1,
170 st_cnt:8, __reserved:8,
171 hs_cnt:8, __reserved1:4;
177 struct nps_host_reg_aux_hw_comply {
180 u32 me:1, le:1, te:1, knc:1, __reserved:28;
186 struct nps_host_reg_aux_lpc {
189 u32 mep:1, __reserved:31;
196 #define REG_GEN_PURP_0 nps_host_reg_non_cl(NPS_CRG_BLKID, 0x1BF)
199 #define REG_GIM_P_INT_EN_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x100)
200 #define REG_GIM_P_INT_POL_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x110)
201 #define REG_GIM_P_INT_SENS_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x114)
202 #define REG_GIM_P_INT_BLK_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x118)
203 #define REG_GIM_P_INT_DST_10 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13A)
204 #define REG_GIM_P_INT_DST_11 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13B)
205 #define REG_GIM_P_INT_DST_25 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x149)
206 #define REG_GIM_P_INT_DST_26 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x14A)
210 .macro GET_CPU_ID reg
211 lr \reg, [CTOP_AUX_LOGIC_GLOBAL_ID]
212 #ifndef CONFIG_EZNPS_MTM_EXT
217 #endif /* __ASSEMBLY__ */
219 #endif /* _PLAT_EZNPS_CTOP_H */