2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * Device Tree for ARC HS Development Kit
14 #include <dt-bindings/net/ti-dp83867.h>
18 compatible = "snps,hsdk";
24 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
33 compatible = "snps,archs38";
40 compatible = "snps,archs38";
47 compatible = "snps,archs38";
54 compatible = "snps,archs38";
62 compatible = "fixed-clock";
63 clock-frequency = <500000000>;
66 cpu_intc: cpu-interrupt-controller {
67 compatible = "snps,archs-intc";
69 #interrupt-cells = <1>;
72 idu_intc: idu-interrupt-controller {
73 compatible = "snps,archs-idu-intc";
75 #interrupt-cells = <1>;
76 interrupt-parent = <&cpu_intc>;
80 compatible = "snps,archs-pct";
83 /* TIMER0 with interrupt for clockevent */
85 compatible = "snps,arc-timer";
87 interrupt-parent = <&cpu_intc>;
91 /* 64-bit Global Free Running Counter */
93 compatible = "snps,archs-timer-gfrc";
98 compatible = "simple-bus";
101 interrupt-parent = <&idu_intc>;
103 ranges = <0x00000000 0xf0000000 0x10000000>;
105 serial: serial@5000 {
106 compatible = "snps,dw-apb-uart";
107 reg = <0x5000 0x100>;
108 clock-frequency = <33330000>;
116 compatible = "fixed-clock";
117 clock-frequency = <400000000>;
121 mmcclk_ciu: mmcclk-ciu {
122 compatible = "fixed-clock";
123 clock-frequency = <100000000>;
127 mmcclk_biu: mmcclk-biu {
128 compatible = "fixed-clock";
129 clock-frequency = <400000000>;
134 #interrupt-cells = <1>;
135 compatible = "snps,dwmac";
136 reg = <0x8000 0x2000>;
138 interrupt-names = "macirq";
142 clock-names = "stmmaceth";
143 phy-handle = <&phy0>;
146 #address-cells = <1>;
148 compatible = "snps,dwmac-mdio";
149 phy0: ethernet-phy@0 {
151 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
152 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
153 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
159 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
160 reg = <0x60000 0x100>;
165 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
166 reg = <0x40000 0x100>;
171 compatible = "altr,socfpga-dw-mshc";
172 reg = <0xa000 0x400>;
175 card-detect-delay = <200>;
176 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
177 clock-names = "biu", "ciu";
184 #address-cells = <1>;
186 device_type = "memory";
187 reg = <0x80000000 0x40000000>; /* 1 GiB */