2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
12 select ARCH_HAS_DMA_COHERENT_TO_PFN
13 select ARCH_HAS_PTE_SPECIAL
14 select ARCH_HAS_SYNC_DMA_FOR_CPU
15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
17 select BUILDTIME_EXTABLE_SORT
18 select CLONE_BACKWARDS
20 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
21 select GENERIC_CLOCKEVENTS
22 select GENERIC_FIND_FIRST_BIT
23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
24 select GENERIC_IRQ_SHOW
25 select GENERIC_PCI_IOMAP
26 select GENERIC_PENDING_IRQ if SMP
27 select GENERIC_SCHED_CLOCK
28 select GENERIC_SMP_IDLE_THREAD
30 select HAVE_ARCH_TRACEHOOK
31 select HAVE_DEBUG_STACKOVERFLOW
32 select HAVE_FUTEX_CMPXCHG if FUTEX
33 select HAVE_GENERIC_DMA_COHERENT
34 select HAVE_IOREMAP_PROT
35 select HAVE_KERNEL_GZIP
36 select HAVE_KERNEL_LZMA
38 select HAVE_KRETPROBES
39 select HAVE_MOD_ARCH_SPECIFIC
41 select HAVE_PERF_EVENTS
42 select HANDLE_DOMAIN_IRQ
44 select MODULES_USE_ELF_RELA
46 select OF_EARLY_FLATTREE
47 select OF_RESERVED_MEM
48 select PCI_SYSCALL if PCI
49 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
51 config ARCH_HAS_CACHE_LINE_SIZE
54 config TRACE_IRQFLAGS_SUPPORT
57 config LOCKDEP_SUPPORT
60 config SCHED_OMIT_FRAME_POINTER
66 config RWSEM_GENERIC_SPINLOCK
69 config ARCH_DISCONTIGMEM_ENABLE
72 config ARCH_FLATMEM_ENABLE
81 config GENERIC_CALIBRATE_DELAY
84 config GENERIC_HWEIGHT
87 config STACKTRACE_SUPPORT
91 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
95 menu "ARC Architecture Configuration"
97 menu "ARC Platform/SoC/Board"
99 source "arch/arc/plat-tb10x/Kconfig"
100 source "arch/arc/plat-axs10x/Kconfig"
101 #New platform adds here
102 source "arch/arc/plat-eznps/Kconfig"
103 source "arch/arc/plat-hsdk/Kconfig"
108 prompt "ARC Instruction Set"
113 select CPU_NO_EFFICIENT_FFS
115 The original ARC ISA of ARC600/700 cores
119 select ARC_TIMERS_64BIT
121 ISA for the Next Generation ARC-HS cores
125 menu "ARC CPU Configuration"
129 default ARC_CPU_770 if ISA_ARCOMPACT
130 default ARC_CPU_HS if ISA_ARCV2
138 Support for ARC750 core
144 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
145 This core has a bunch of cool new features:
146 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
147 Shared Address Spaces (for sharing TLB entries in MMU)
148 -Caches: New Prog Model, Region Flush
149 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
157 Support for ARC HS38x Cores based on ARCv2 ISA
158 The notable features are:
159 - SMP configurations of upto 4 core with coherency
160 - Optional L2 Cache and IO-Coherency
161 - Revised Interrupt Architecture (multiple priorites, reg banks,
162 auto stack switch, auto regfile save/restore)
163 - MMUv4 (PIPT dcache, Huge Pages)
165 * 64bit load/store: LDD, STD
166 * Hardware assisted divide/remainder: DIV, REM
167 * Function prologue/epilogue: ENTER_S, LEAVE_S
168 * IRQ enable/disable: CLRI, SETI
169 * pop count: FFS, FLS
170 * SETcc, BMSKN, XBFU...
174 config CPU_BIG_ENDIAN
175 bool "Enable Big Endian Mode"
177 Build kernel for Big Endian Mode of ARC CPU
180 bool "Symmetric Multi-Processing"
181 select ARC_MCIP if ISA_ARCV2
183 This enables support for systems with more than one CPU.
188 int "Maximum number of CPUs (2-4096)"
192 config ARC_SMP_HALT_ON_RESET
193 bool "Enable Halt-on-reset boot mode"
194 default y if ARC_UBOOT_SUPPORT
196 In SMP configuration cores can be configured as Halt-on-reset
197 or they could all start at same time. For Halt-on-reset, non
198 masters are parked until Master kicks them so they can start of
199 at designated entry point. For other case, all jump to common
200 entry point and spin wait for Master's signal.
205 bool "ARConnect Multicore IP (MCIP) Support "
209 This IP block enables SMP in ARC-HS38 cores.
210 It provides for cross-core interrupts, multi-core debug
211 hardware semaphores, shared memory,....
214 bool "Enable Cache Support"
219 config ARC_CACHE_LINE_SHIFT
220 int "Cache Line Length (as power of 2)"
224 Starting with ARC700 4.9, Cache line length is configurable,
225 This option specifies "N", with Line-len = 2 power N
226 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
227 Linux only supports same line lengths for I and D caches.
229 config ARC_HAS_ICACHE
230 bool "Use Instruction Cache"
233 config ARC_HAS_DCACHE
234 bool "Use Data Cache"
237 config ARC_CACHE_PAGES
238 bool "Per Page Cache Control"
240 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
242 This can be used to over-ride the global I/D Cache Enable on a
243 per-page basis (but only for pages accessed via MMU such as
244 Kernel Virtual address or User Virtual Address)
245 TLB entries have a per-page Cache Enable Bit.
246 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
247 Global DISABLE + Per Page ENABLE won't work
249 config ARC_CACHE_VIPT_ALIASING
250 bool "Support VIPT Aliasing D$"
251 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
258 Single Cycle RAMS to store Fast Path Code
261 int "ICCM Size in KB"
263 depends on ARC_HAS_ICCM
268 Single Cycle RAMS to store Fast Path Data
271 int "DCCM Size in KB"
273 depends on ARC_HAS_DCCM
276 hex "DCCM map address"
278 depends on ARC_HAS_DCCM
282 default ARC_MMU_V3 if ARC_CPU_770
283 default ARC_MMU_V2 if ARC_CPU_750D
284 default ARC_MMU_V4 if ARC_CPU_HS
296 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
297 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
301 depends on ARC_CPU_770
303 Introduced with ARC700 4.10: New Features
304 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
305 Shared Address Spaces (SASID)
317 prompt "MMU Page Size"
318 default ARC_PAGE_SIZE_8K
320 config ARC_PAGE_SIZE_8K
323 Choose between 8k vs 16k
325 config ARC_PAGE_SIZE_16K
327 depends on ARC_MMU_V3 || ARC_MMU_V4
329 config ARC_PAGE_SIZE_4K
331 depends on ARC_MMU_V3 || ARC_MMU_V4
336 prompt "MMU Super Page Size"
337 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
338 default ARC_HUGEPAGE_2M
340 config ARC_HUGEPAGE_2M
343 config ARC_HUGEPAGE_16M
349 int "Maximum NUMA Nodes (as a power of 2)"
350 default "0" if !DISCONTIGMEM
351 default "1" if DISCONTIGMEM
352 depends on NEED_MULTIPLE_NODES
354 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
359 config ARC_COMPACT_IRQ_LEVELS
360 bool "Setup Timer IRQ as high Priority"
361 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
364 config ARC_FPU_SAVE_RESTORE
365 bool "Enable FPU state persistence across context switch"
367 Double Precision Floating Point unit had dedicated regs which
368 need to be saved/restored across context-switch.
369 Note that ARC FPU is overly simplistic, unlike say x86, which has
370 hardware pieces to allow software to conditionally save/restore,
371 based on actual usage of FPU by a task. Thus our implemn does
372 this for all tasks in system.
380 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
382 depends on !ARC_CANT_LLSC
385 bool "Insn: SWAPE (endian-swap)"
391 bool "Insn: 64bit LDD/STD"
393 Enable gcc to generate 64-bit load/store instructions
394 ISA mandates even/odd registers to allow encoding of two
395 dest operands with 2 possible source operands.
398 config ARC_HAS_DIV_REM
399 bool "Insn: div, divu, rem, remu"
402 config ARC_HAS_ACCL_REGS
403 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
406 Depending on the configuration, CPU can contain accumulator reg-pair
407 (also referred to as r58:r59). These can also be used by gcc as GPR so
408 kernel needs to save/restore per process
412 endmenu # "ARC CPU Configuration"
414 config LINUX_LINK_BASE
415 hex "Kernel link address"
418 ARC700 divides the 32 bit phy address space into two equal halves
419 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
420 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
421 Typically Linux kernel is linked at the start of untransalted addr,
422 hence the default value of 0x8zs.
423 However some customers have peripherals mapped at this addr, so
424 Linux needs to be scooted a bit.
425 If you don't know what the above means, leave this setting alone.
426 This needs to match memory start address specified in Device Tree
428 config LINUX_RAM_BASE
429 hex "RAM base address"
430 default LINUX_LINK_BASE
432 By default Linux is linked at base of RAM. However in some special
433 cases (such as HSDK), Linux can't be linked at start of DDR, hence
437 bool "High Memory Support"
438 select ARCH_DISCONTIGMEM_ENABLE
440 With ARC 2G:2G address split, only upper 2G is directly addressable by
441 kernel. Enable this to potentially allow access to rest of 2G and PAE
445 bool "Support for the 40-bit Physical Address Extension"
448 select PHYS_ADDR_T_64BIT
450 Enable access to physical memory beyond 4G, only supported on
451 ARC cores with 40 bit Physical Addressing support
453 config ARC_KVADDR_SIZE
454 int "Kernel Virtual Address Space size (MB)"
458 The kernel address space is carved out of 256MB of translated address
459 space for catering to vmalloc, modules, pkmap, fixmap. This however may
460 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
461 this to be stretched to 512 MB (by extending into the reserved
464 config ARC_CURR_IN_REG
465 bool "Dedicate Register r25 for current_task pointer"
468 This reserved Register R25 to point to Current Task in
469 kernel mode. This saves memory access for each such access
472 config ARC_EMUL_UNALIGNED
473 bool "Emulate unaligned memory access (userspace only)"
474 select SYSCTL_ARCH_UNALIGN_NO_WARN
475 select SYSCTL_ARCH_UNALIGN_ALLOW
476 depends on ISA_ARCOMPACT
478 This enables misaligned 16 & 32 bit memory access from user space.
479 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
480 potential bugs in code
483 int "Timer Frequency"
486 config ARC_METAWARE_HLINK
487 bool "Support for Metaware debugger assisted Host access"
489 This options allows a Linux userland apps to directly access
490 host file system (open/creat/read/write etc) with help from
491 Metaware Debugger. This can come in handy for Linux-host communication
492 when there is no real usable peripheral such as EMAC.
500 config ARC_DW2_UNWIND
501 bool "Enable DWARF specific kernel stack unwind"
505 Compiles the kernel with DWARF unwind information and can be used
506 to get stack backtraces.
508 If you say Y here the resulting kernel image will be slightly larger
509 but not slower, and it will give very useful debugging information.
510 If you don't debug the kernel, you can say N, but we may not be able
511 to solve problems without frame unwind information
513 config ARC_DBG_TLB_PARANOIA
514 bool "Paranoia Checks in Low Level TLB Handlers"
518 config ARC_UBOOT_SUPPORT
519 bool "Support uboot arg Handling"
521 ARC Linux by default checks for uboot provided args as pointers to
522 external cmdline or DTB. This however breaks in absence of uboot,
523 when booting from Metaware debugger directly, as the registers are
524 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
525 registers look like uboot args to kernel which then chokes.
526 So only enable the uboot arg checking/processing if users are sure
527 of uboot being in play.
529 config ARC_BUILTIN_DTB_NAME
530 string "Built in DTB"
532 Set the name of the DTB to embed in the vmlinux binary
533 Leaving it blank selects the minimal "skeleton" dtb
535 endmenu # "ARC Architecture Configuration"
537 config FORCE_MAX_ZONEORDER
538 int "Maximum zone order"
539 default "12" if ARC_HUGEPAGE_16M
542 source "kernel/power/Kconfig"