1 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
5 By: David Howells <dhowells@redhat.com>
6 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
10 (*) Abstract memory access model.
15 (*) What are memory barriers?
17 - Varieties of memory barrier.
18 - What may not be assumed about memory barriers?
19 - Data dependency barriers.
20 - Control dependencies.
21 - SMP barrier pairing.
22 - Examples of memory barrier sequences.
23 - Read memory barriers vs load speculation.
26 (*) Explicit kernel barriers.
29 - CPU memory barriers.
32 (*) Implicit kernel memory barriers.
35 - Interrupt disabling functions.
36 - Sleep and wake-up functions.
37 - Miscellaneous functions.
39 (*) Inter-CPU locking barrier effects.
41 - Locks vs memory accesses.
42 - Locks vs I/O accesses.
44 (*) Where are memory barriers needed?
46 - Interprocessor interaction.
51 (*) Kernel I/O barrier effects.
53 (*) Assumed minimum execution ordering model.
55 (*) The effects of the cpu cache.
58 - Cache coherency vs DMA.
59 - Cache coherency vs MMIO.
61 (*) The things CPUs get up to.
63 - And then there's the Alpha.
72 ============================
73 ABSTRACT MEMORY ACCESS MODEL
74 ============================
76 Consider the following abstract model of the system:
81 +-------+ : +--------+ : +-------+
84 | CPU 1 |<----->| Memory |<----->| CPU 2 |
87 +-------+ : +--------+ : +-------+
95 +---------->| Device |<----------+
101 Each CPU executes a program that generates memory access operations. In the
102 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
103 perform the memory operations in any order it likes, provided program causality
104 appears to be maintained. Similarly, the compiler may also arrange the
105 instructions it emits in any order it likes, provided it doesn't affect the
106 apparent operation of the program.
108 So in the above diagram, the effects of the memory operations performed by a
109 CPU are perceived by the rest of the system as the operations cross the
110 interface between the CPU and rest of the system (the dotted lines).
113 For example, consider the following sequence of events:
116 =============== ===============
121 The set of accesses as seen by the memory system in the middle can be arranged
122 in 24 different combinations:
124 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
125 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
126 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
127 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
128 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
129 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
130 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
134 and can thus result in four different combinations of values:
142 Furthermore, the stores committed by a CPU to the memory system may not be
143 perceived by the loads made by another CPU in the same order as the stores were
147 As a further example, consider this sequence of events:
150 =============== ===============
151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
155 There is an obvious data dependency here, as the value loaded into D depends on
156 the address retrieved from P by CPU 2. At the end of the sequence, any of the
157 following results are possible:
159 (Q == &A) and (D == 1)
160 (Q == &B) and (D == 2)
161 (Q == &B) and (D == 4)
163 Note that CPU 2 will never try and load C into D because the CPU will load P
164 into Q before issuing the load of *Q.
170 Some devices present their control interfaces as collections of memory
171 locations, but the order in which the control registers are accessed is very
172 important. For instance, imagine an ethernet card with a set of internal
173 registers that are accessed through an address port register (A) and a data
174 port register (D). To read internal register 5, the following code might then
180 but this might show up as either of the following two sequences:
182 STORE *A = 5, x = LOAD *D
183 x = LOAD *D, STORE *A = 5
185 the second of which will almost certainly result in a malfunction, since it set
186 the address _after_ attempting to read the register.
192 There are some minimal guarantees that may be expected of a CPU:
194 (*) On any given CPU, dependent memory accesses will be issued in order, with
195 respect to itself. This means that for:
197 Q = READ_ONCE(P); smp_read_barrier_depends(); D = READ_ONCE(*Q);
199 the CPU will issue the following memory operations:
201 Q = LOAD P, D = LOAD *Q
203 and always in that order. On most systems, smp_read_barrier_depends()
204 does nothing, but it is required for DEC Alpha. The READ_ONCE()
205 is required to prevent compiler mischief. Please note that you
206 should normally use something like rcu_dereference() instead of
207 open-coding smp_read_barrier_depends().
209 (*) Overlapping loads and stores within a particular CPU will appear to be
210 ordered within that CPU. This means that for:
212 a = READ_ONCE(*X); WRITE_ONCE(*X, b);
214 the CPU will only issue the following sequence of memory operations:
216 a = LOAD *X, STORE *X = b
220 WRITE_ONCE(*X, c); d = READ_ONCE(*X);
222 the CPU will only issue:
224 STORE *X = c, d = LOAD *X
226 (Loads and stores overlap if they are targeted at overlapping pieces of
229 And there are a number of things that _must_ or _must_not_ be assumed:
231 (*) It _must_not_ be assumed that the compiler will do what you want
232 with memory references that are not protected by READ_ONCE() and
233 WRITE_ONCE(). Without them, the compiler is within its rights to
234 do all sorts of "creative" transformations, which are covered in
235 the COMPILER BARRIER section.
237 (*) It _must_not_ be assumed that independent loads and stores will be issued
238 in the order given. This means that for:
240 X = *A; Y = *B; *D = Z;
242 we may get any of the following sequences:
244 X = LOAD *A, Y = LOAD *B, STORE *D = Z
245 X = LOAD *A, STORE *D = Z, Y = LOAD *B
246 Y = LOAD *B, X = LOAD *A, STORE *D = Z
247 Y = LOAD *B, STORE *D = Z, X = LOAD *A
248 STORE *D = Z, X = LOAD *A, Y = LOAD *B
249 STORE *D = Z, Y = LOAD *B, X = LOAD *A
251 (*) It _must_ be assumed that overlapping memory accesses may be merged or
252 discarded. This means that for:
254 X = *A; Y = *(A + 4);
256 we may get any one of the following sequences:
258 X = LOAD *A; Y = LOAD *(A + 4);
259 Y = LOAD *(A + 4); X = LOAD *A;
260 {X, Y} = LOAD {*A, *(A + 4) };
264 *A = X; *(A + 4) = Y;
268 STORE *A = X; STORE *(A + 4) = Y;
269 STORE *(A + 4) = Y; STORE *A = X;
270 STORE {*A, *(A + 4) } = {X, Y};
272 And there are anti-guarantees:
274 (*) These guarantees do not apply to bitfields, because compilers often
275 generate code to modify these using non-atomic read-modify-write
276 sequences. Do not attempt to use bitfields to synchronize parallel
279 (*) Even in cases where bitfields are protected by locks, all fields
280 in a given bitfield must be protected by one lock. If two fields
281 in a given bitfield are protected by different locks, the compiler's
282 non-atomic read-modify-write sequences can cause an update to one
283 field to corrupt the value of an adjacent field.
285 (*) These guarantees apply only to properly aligned and sized scalar
286 variables. "Properly sized" currently means variables that are
287 the same size as "char", "short", "int" and "long". "Properly
288 aligned" means the natural alignment, thus no constraints for
289 "char", two-byte alignment for "short", four-byte alignment for
290 "int", and either four-byte or eight-byte alignment for "long",
291 on 32-bit and 64-bit systems, respectively. Note that these
292 guarantees were introduced into the C11 standard, so beware when
293 using older pre-C11 compilers (for example, gcc 4.6). The portion
294 of the standard containing this guarantee is Section 3.14, which
295 defines "memory location" as follows:
298 either an object of scalar type, or a maximal sequence
299 of adjacent bit-fields all having nonzero width
301 NOTE 1: Two threads of execution can update and access
302 separate memory locations without interfering with
305 NOTE 2: A bit-field and an adjacent non-bit-field member
306 are in separate memory locations. The same applies
307 to two bit-fields, if one is declared inside a nested
308 structure declaration and the other is not, or if the two
309 are separated by a zero-length bit-field declaration,
310 or if they are separated by a non-bit-field member
311 declaration. It is not safe to concurrently update two
312 bit-fields in the same structure if all members declared
313 between them are also bit-fields, no matter what the
314 sizes of those intervening bit-fields happen to be.
317 =========================
318 WHAT ARE MEMORY BARRIERS?
319 =========================
321 As can be seen above, independent memory operations are effectively performed
322 in random order, but this can be a problem for CPU-CPU interaction and for I/O.
323 What is required is some way of intervening to instruct the compiler and the
324 CPU to restrict the order.
326 Memory barriers are such interventions. They impose a perceived partial
327 ordering over the memory operations on either side of the barrier.
329 Such enforcement is important because the CPUs and other devices in a system
330 can use a variety of tricks to improve performance, including reordering,
331 deferral and combination of memory operations; speculative loads; speculative
332 branch prediction and various types of caching. Memory barriers are used to
333 override or suppress these tricks, allowing the code to sanely control the
334 interaction of multiple CPUs and/or devices.
337 VARIETIES OF MEMORY BARRIER
338 ---------------------------
340 Memory barriers come in four basic varieties:
342 (1) Write (or store) memory barriers.
344 A write memory barrier gives a guarantee that all the STORE operations
345 specified before the barrier will appear to happen before all the STORE
346 operations specified after the barrier with respect to the other
347 components of the system.
349 A write barrier is a partial ordering on stores only; it is not required
350 to have any effect on loads.
352 A CPU can be viewed as committing a sequence of store operations to the
353 memory system as time progresses. All stores before a write barrier will
354 occur in the sequence _before_ all the stores after the write barrier.
356 [!] Note that write barriers should normally be paired with read or data
357 dependency barriers; see the "SMP barrier pairing" subsection.
360 (2) Data dependency barriers.
362 A data dependency barrier is a weaker form of read barrier. In the case
363 where two loads are performed such that the second depends on the result
364 of the first (eg: the first load retrieves the address to which the second
365 load will be directed), a data dependency barrier would be required to
366 make sure that the target of the second load is updated before the address
367 obtained by the first load is accessed.
369 A data dependency barrier is a partial ordering on interdependent loads
370 only; it is not required to have any effect on stores, independent loads
371 or overlapping loads.
373 As mentioned in (1), the other CPUs in the system can be viewed as
374 committing sequences of stores to the memory system that the CPU being
375 considered can then perceive. A data dependency barrier issued by the CPU
376 under consideration guarantees that for any load preceding it, if that
377 load touches one of a sequence of stores from another CPU, then by the
378 time the barrier completes, the effects of all the stores prior to that
379 touched by the load will be perceptible to any loads issued after the data
382 See the "Examples of memory barrier sequences" subsection for diagrams
383 showing the ordering constraints.
385 [!] Note that the first load really has to have a _data_ dependency and
386 not a control dependency. If the address for the second load is dependent
387 on the first load, but the dependency is through a conditional rather than
388 actually loading the address itself, then it's a _control_ dependency and
389 a full read barrier or better is required. See the "Control dependencies"
390 subsection for more information.
392 [!] Note that data dependency barriers should normally be paired with
393 write barriers; see the "SMP barrier pairing" subsection.
396 (3) Read (or load) memory barriers.
398 A read barrier is a data dependency barrier plus a guarantee that all the
399 LOAD operations specified before the barrier will appear to happen before
400 all the LOAD operations specified after the barrier with respect to the
401 other components of the system.
403 A read barrier is a partial ordering on loads only; it is not required to
404 have any effect on stores.
406 Read memory barriers imply data dependency barriers, and so can substitute
409 [!] Note that read barriers should normally be paired with write barriers;
410 see the "SMP barrier pairing" subsection.
413 (4) General memory barriers.
415 A general memory barrier gives a guarantee that all the LOAD and STORE
416 operations specified before the barrier will appear to happen before all
417 the LOAD and STORE operations specified after the barrier with respect to
418 the other components of the system.
420 A general memory barrier is a partial ordering over both loads and stores.
422 General memory barriers imply both read and write memory barriers, and so
423 can substitute for either.
426 And a couple of implicit varieties:
428 (5) ACQUIRE operations.
430 This acts as a one-way permeable barrier. It guarantees that all memory
431 operations after the ACQUIRE operation will appear to happen after the
432 ACQUIRE operation with respect to the other components of the system.
433 ACQUIRE operations include LOCK operations and smp_load_acquire()
436 Memory operations that occur before an ACQUIRE operation may appear to
437 happen after it completes.
439 An ACQUIRE operation should almost always be paired with a RELEASE
443 (6) RELEASE operations.
445 This also acts as a one-way permeable barrier. It guarantees that all
446 memory operations before the RELEASE operation will appear to happen
447 before the RELEASE operation with respect to the other components of the
448 system. RELEASE operations include UNLOCK operations and
449 smp_store_release() operations.
451 Memory operations that occur after a RELEASE operation may appear to
452 happen before it completes.
454 The use of ACQUIRE and RELEASE operations generally precludes the need
455 for other sorts of memory barrier (but note the exceptions mentioned in
456 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
457 pair is -not- guaranteed to act as a full memory barrier. However, after
458 an ACQUIRE on a given variable, all memory accesses preceding any prior
459 RELEASE on that same variable are guaranteed to be visible. In other
460 words, within a given variable's critical section, all accesses of all
461 previous critical sections for that variable are guaranteed to have
464 This means that ACQUIRE acts as a minimal "acquire" operation and
465 RELEASE acts as a minimal "release" operation.
468 Memory barriers are only required where there's a possibility of interaction
469 between two CPUs or between a CPU and a device. If it can be guaranteed that
470 there won't be any such interaction in any particular piece of code, then
471 memory barriers are unnecessary in that piece of code.
474 Note that these are the _minimum_ guarantees. Different architectures may give
475 more substantial guarantees, but they may _not_ be relied upon outside of arch
479 WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
480 ----------------------------------------------
482 There are certain things that the Linux kernel memory barriers do not guarantee:
484 (*) There is no guarantee that any of the memory accesses specified before a
485 memory barrier will be _complete_ by the completion of a memory barrier
486 instruction; the barrier can be considered to draw a line in that CPU's
487 access queue that accesses of the appropriate type may not cross.
489 (*) There is no guarantee that issuing a memory barrier on one CPU will have
490 any direct effect on another CPU or any other hardware in the system. The
491 indirect effect will be the order in which the second CPU sees the effects
492 of the first CPU's accesses occur, but see the next point:
494 (*) There is no guarantee that a CPU will see the correct order of effects
495 from a second CPU's accesses, even _if_ the second CPU uses a memory
496 barrier, unless the first CPU _also_ uses a matching memory barrier (see
497 the subsection on "SMP Barrier Pairing").
499 (*) There is no guarantee that some intervening piece of off-the-CPU
500 hardware[*] will not reorder the memory accesses. CPU cache coherency
501 mechanisms should propagate the indirect effects of a memory barrier
502 between CPUs, but might not do so in order.
504 [*] For information on bus mastering DMA and coherency please read:
506 Documentation/PCI/pci.txt
507 Documentation/DMA-API-HOWTO.txt
508 Documentation/DMA-API.txt
511 DATA DEPENDENCY BARRIERS
512 ------------------------
514 The usage requirements of data dependency barriers are a little subtle, and
515 it's not always obvious that they're needed. To illustrate, consider the
516 following sequence of events:
519 =============== ===============
520 { A == 1, B == 2, C = 3, P == &A, Q == &C }
527 There's a clear data dependency here, and it would seem that by the end of the
528 sequence, Q must be either &A or &B, and that:
530 (Q == &A) implies (D == 1)
531 (Q == &B) implies (D == 4)
533 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
534 leading to the following situation:
536 (Q == &B) and (D == 2) ????
538 Whilst this may seem like a failure of coherency or causality maintenance, it
539 isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
542 To deal with this, a data dependency barrier or better must be inserted
543 between the address load and the data load:
546 =============== ===============
547 { A == 1, B == 2, C = 3, P == &A, Q == &C }
552 <data dependency barrier>
555 This enforces the occurrence of one of the two implications, and prevents the
556 third possibility from arising.
558 A data-dependency barrier must also order against dependent writes:
561 =============== ===============
562 { A == 1, B == 2, C = 3, P == &A, Q == &C }
567 <data dependency barrier>
570 The data-dependency barrier must order the read into Q with the store
571 into *Q. This prohibits this outcome:
575 Please note that this pattern should be rare. After all, the whole point
576 of dependency ordering is to -prevent- writes to the data structure, along
577 with the expensive cache misses associated with those writes. This pattern
578 can be used to record rare error conditions and the like, and the ordering
579 prevents such records from being lost.
582 [!] Note that this extremely counterintuitive situation arises most easily on
583 machines with split caches, so that, for example, one cache bank processes
584 even-numbered cache lines and the other bank processes odd-numbered cache
585 lines. The pointer P might be stored in an odd-numbered cache line, and the
586 variable B might be stored in an even-numbered cache line. Then, if the
587 even-numbered bank of the reading CPU's cache is extremely busy while the
588 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
589 but the old value of the variable B (2).
592 The data dependency barrier is very important to the RCU system,
593 for example. See rcu_assign_pointer() and rcu_dereference() in
594 include/linux/rcupdate.h. This permits the current target of an RCU'd
595 pointer to be replaced with a new modified target, without the replacement
596 target appearing to be incompletely initialised.
598 See also the subsection on "Cache Coherency" for a more thorough example.
604 A load-load control dependency requires a full read memory barrier, not
605 simply a data dependency barrier to make it work correctly. Consider the
606 following bit of code:
610 <data dependency barrier> /* BUG: No data dependency!!! */
614 This will not have the desired effect because there is no actual data
615 dependency, but rather a control dependency that the CPU may short-circuit
616 by attempting to predict the outcome in advance, so that other CPUs see
617 the load from b as having happened before the load from a. In such a
618 case what's actually required is:
626 However, stores are not speculated. This means that ordering -is- provided
627 for load-store control dependencies, as in the following example:
634 Control dependencies pair normally with other types of barriers. That
635 said, please note that READ_ONCE() is not optional! Without the
636 READ_ONCE(), the compiler might combine the load from 'a' with other
637 loads from 'a', and the store to 'b' with other stores to 'b', with
638 possible highly counterintuitive effects on ordering.
640 Worse yet, if the compiler is able to prove (say) that the value of
641 variable 'a' is always non-zero, it would be well within its rights
642 to optimize the original example by eliminating the "if" statement
646 b = p; /* BUG: Compiler and CPU can both reorder!!! */
648 So don't leave out the READ_ONCE().
650 It is tempting to try to enforce ordering on identical stores on both
651 branches of the "if" statement as follows:
664 Unfortunately, current compilers will transform this as follows at high
669 WRITE_ONCE(b, p); /* BUG: No ordering vs. load from a!!! */
671 /* WRITE_ONCE(b, p); -- moved up, BUG!!! */
674 /* WRITE_ONCE(b, p); -- moved up, BUG!!! */
678 Now there is no conditional between the load from 'a' and the store to
679 'b', which means that the CPU is within its rights to reorder them:
680 The conditional is absolutely required, and must be present in the
681 assembly code even after all compiler optimizations have been applied.
682 Therefore, if you need ordering in this example, you need explicit
683 memory barriers, for example, smp_store_release():
687 smp_store_release(&b, p);
690 smp_store_release(&b, p);
694 In contrast, without explicit memory barriers, two-legged-if control
695 ordering is guaranteed only when the stores differ, for example:
706 The initial READ_ONCE() is still required to prevent the compiler from
707 proving the value of 'a'.
709 In addition, you need to be careful what you do with the local variable 'q',
710 otherwise the compiler might be able to guess the value and again remove
711 the needed conditional. For example:
722 If MAX is defined to be 1, then the compiler knows that (q % MAX) is
723 equal to zero, in which case the compiler is within its rights to
724 transform the above code into the following:
730 Given this transformation, the CPU is not required to respect the ordering
731 between the load from variable 'a' and the store to variable 'b'. It is
732 tempting to add a barrier(), but this does not help. The conditional
733 is gone, and the barrier won't bring it back. Therefore, if you are
734 relying on this ordering, you should make sure that MAX is greater than
735 one, perhaps as follows:
738 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
747 Please note once again that the stores to 'b' differ. If they were
748 identical, as noted earlier, the compiler could pull this store outside
749 of the 'if' statement.
751 You must also be careful not to rely too much on boolean short-circuit
752 evaluation. Consider this example:
758 Because the first condition cannot fault and the second condition is
759 always true, the compiler can transform this example as following,
760 defeating control dependency:
765 This example underscores the need to ensure that the compiler cannot
766 out-guess your code. More generally, although READ_ONCE() does force
767 the compiler to actually emit code for a given load, it does not force
768 the compiler to use the results.
770 Finally, control dependencies do -not- provide transitivity. This is
771 demonstrated by two related examples, with the initial values of
772 x and y both being zero:
775 ======================= =======================
776 r1 = READ_ONCE(x); r2 = READ_ONCE(y);
777 if (r1 > 0) if (r2 > 0)
778 WRITE_ONCE(y, 1); WRITE_ONCE(x, 1);
780 assert(!(r1 == 1 && r2 == 1));
782 The above two-CPU example will never trigger the assert(). However,
783 if control dependencies guaranteed transitivity (which they do not),
784 then adding the following CPU would guarantee a related assertion:
787 =====================
790 assert(!(r1 == 2 && r2 == 1 && x == 2)); /* FAILS!!! */
792 But because control dependencies do -not- provide transitivity, the above
793 assertion can fail after the combined three-CPU example completes. If you
794 need the three-CPU example to provide ordering, you will need smp_mb()
795 between the loads and stores in the CPU 0 and CPU 1 code fragments,
796 that is, just before or just after the "if" statements. Furthermore,
797 the original two-CPU example is very fragile and should be avoided.
799 These two examples are the LB and WWC litmus tests from this paper:
800 http://www.cl.cam.ac.uk/users/pes20/ppc-supplemental/test6.pdf and this
801 site: https://www.cl.cam.ac.uk/~pes20/ppcmem/index.html.
805 (*) Control dependencies can order prior loads against later stores.
806 However, they do -not- guarantee any other sort of ordering:
807 Not prior loads against later loads, nor prior stores against
808 later anything. If you need these other forms of ordering,
809 use smp_rmb(), smp_wmb(), or, in the case of prior stores and
810 later loads, smp_mb().
812 (*) If both legs of the "if" statement begin with identical stores to
813 the same variable, then those stores must be ordered, either by
814 preceding both of them with smp_mb() or by using smp_store_release()
815 to carry out the stores. Please note that it is -not- sufficient
816 to use barrier() at beginning of each leg of the "if" statement,
817 as optimizing compilers do not necessarily respect barrier()
820 (*) Control dependencies require at least one run-time conditional
821 between the prior load and the subsequent store, and this
822 conditional must involve the prior load. If the compiler is able
823 to optimize the conditional away, it will have also optimized
824 away the ordering. Careful use of READ_ONCE() and WRITE_ONCE()
825 can help to preserve the needed conditional.
827 (*) Control dependencies require that the compiler avoid reordering the
828 dependency into nonexistence. Careful use of READ_ONCE() or
829 atomic{,64}_read() can help to preserve your control dependency.
830 Please see the COMPILER BARRIER section for more information.
832 (*) Control dependencies pair normally with other types of barriers.
834 (*) Control dependencies do -not- provide transitivity. If you
835 need transitivity, use smp_mb().
841 When dealing with CPU-CPU interactions, certain types of memory barrier should
842 always be paired. A lack of appropriate pairing is almost certainly an error.
844 General barriers pair with each other, though they also pair with most
845 other types of barriers, albeit without transitivity. An acquire barrier
846 pairs with a release barrier, but both may also pair with other barriers,
847 including of course general barriers. A write barrier pairs with a data
848 dependency barrier, a control dependency, an acquire barrier, a release
849 barrier, a read barrier, or a general barrier. Similarly a read barrier,
850 control dependency, or a data dependency barrier pairs with a write
851 barrier, an acquire barrier, a release barrier, or a general barrier:
854 =============== ===============
857 WRITE_ONCE(b, 2); x = READ_ONCE(b);
864 =============== ===============================
867 WRITE_ONCE(b, &a); x = READ_ONCE(b);
868 <data dependency barrier>
874 =============== ===============================
877 WRITE_ONCE(y, 1); if (r2 = READ_ONCE(x)) {
878 <implicit control dependency>
882 assert(r1 == 0 || r2 == 0);
884 Basically, the read barrier always has to be there, even though it can be of
887 [!] Note that the stores before the write barrier would normally be expected to
888 match the loads after the read barrier or the data dependency barrier, and vice
892 =================== ===================
893 WRITE_ONCE(a, 1); }---- --->{ v = READ_ONCE(c);
894 WRITE_ONCE(b, 2); } \ / { w = READ_ONCE(d);
895 <write barrier> \ <read barrier>
896 WRITE_ONCE(c, 3); } / \ { x = READ_ONCE(a);
897 WRITE_ONCE(d, 4); }---- --->{ y = READ_ONCE(b);
900 EXAMPLES OF MEMORY BARRIER SEQUENCES
901 ------------------------------------
903 Firstly, write barriers act as partial orderings on store operations.
904 Consider the following sequence of events:
907 =======================
915 This sequence of events is committed to the memory coherence system in an order
916 that the rest of the system might perceive as the unordered set of { STORE A,
917 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
922 | |------>| C=3 | } /\
923 | | : +------+ }----- \ -----> Events perceptible to
924 | | : | A=1 | } \/ the rest of the system
926 | CPU 1 | : | B=2 | }
928 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
929 | | +------+ } requires all stores prior to the
930 | | : | E=5 | } barrier to be committed before
931 | | : +------+ } further stores may take place
936 | Sequence in which stores are committed to the
937 | memory system by CPU 1
941 Secondly, data dependency barriers act as partial orderings on data-dependent
942 loads. Consider the following sequence of events:
945 ======================= =======================
946 { B = 7; X = 9; Y = 8; C = &Y }
951 STORE D = 4 LOAD C (gets &B)
954 Without intervention, CPU 2 may perceive the events on CPU 1 in some
955 effectively random order, despite the write barrier issued by CPU 1:
958 | | +------+ +-------+ | Sequence of update
959 | |------>| B=2 |----- --->| Y->8 | | of perception on
960 | | : +------+ \ +-------+ | CPU 2
961 | CPU 1 | : | A=1 | \ --->| C->&Y | V
962 | | +------+ | +-------+
963 | | wwwwwwwwwwwwwwww | : :
965 | | : | C=&B |--- | : : +-------+
966 | | : +------+ \ | +-------+ | |
967 | |------>| D=4 | ----------->| C->&B |------>| |
968 | | +------+ | +-------+ | |
969 +-------+ : : | : : | |
973 Apparently incorrect ---> | | B->7 |------>| |
974 perception of B (!) | +-------+ | |
977 The load of X holds ---> \ | X->9 |------>| |
978 up the maintenance \ +-------+ | |
979 of coherence of B ----->| B->2 | +-------+
984 In the above example, CPU 2 perceives that B is 7, despite the load of *C
985 (which would be B) coming after the LOAD of C.
987 If, however, a data dependency barrier were to be placed between the load of C
988 and the load of *C (ie: B) on CPU 2:
991 ======================= =======================
992 { B = 7; X = 9; Y = 8; C = &Y }
997 STORE D = 4 LOAD C (gets &B)
998 <data dependency barrier>
1001 then the following will occur:
1004 | | +------+ +-------+
1005 | |------>| B=2 |----- --->| Y->8 |
1006 | | : +------+ \ +-------+
1007 | CPU 1 | : | A=1 | \ --->| C->&Y |
1008 | | +------+ | +-------+
1009 | | wwwwwwwwwwwwwwww | : :
1011 | | : | C=&B |--- | : : +-------+
1012 | | : +------+ \ | +-------+ | |
1013 | |------>| D=4 | ----------->| C->&B |------>| |
1014 | | +------+ | +-------+ | |
1015 +-------+ : : | : : | |
1019 | | X->9 |------>| |
1021 Makes sure all effects ---> \ ddddddddddddddddd | |
1022 prior to the store of C \ +-------+ | |
1023 are perceptible to ----->| B->2 |------>| |
1024 subsequent loads +-------+ | |
1028 And thirdly, a read barrier acts as a partial order on loads. Consider the
1029 following sequence of events:
1032 ======================= =======================
1040 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1041 some effectively random order, despite the write barrier issued by CPU 1:
1044 | | +------+ +-------+
1045 | |------>| A=1 |------ --->| A->0 |
1046 | | +------+ \ +-------+
1047 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1048 | | +------+ | +-------+
1049 | |------>| B=2 |--- | : :
1050 | | +------+ \ | : : +-------+
1051 +-------+ : : \ | +-------+ | |
1052 ---------->| B->2 |------>| |
1053 | +-------+ | CPU 2 |
1054 | | A->0 |------>| |
1064 If, however, a read barrier were to be placed between the load of B and the
1068 ======================= =======================
1077 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
1081 | | +------+ +-------+
1082 | |------>| A=1 |------ --->| A->0 |
1083 | | +------+ \ +-------+
1084 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1085 | | +------+ | +-------+
1086 | |------>| B=2 |--- | : :
1087 | | +------+ \ | : : +-------+
1088 +-------+ : : \ | +-------+ | |
1089 ---------->| B->2 |------>| |
1090 | +-------+ | CPU 2 |
1093 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1094 barrier causes all effects \ +-------+ | |
1095 prior to the storage of B ---->| A->1 |------>| |
1096 to be perceptible to CPU 2 +-------+ | |
1100 To illustrate this more completely, consider what could happen if the code
1101 contained a load of A either side of the read barrier:
1104 ======================= =======================
1110 LOAD A [first load of A]
1112 LOAD A [second load of A]
1114 Even though the two loads of A both occur after the load of B, they may both
1115 come up with different values:
1118 | | +------+ +-------+
1119 | |------>| A=1 |------ --->| A->0 |
1120 | | +------+ \ +-------+
1121 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1122 | | +------+ | +-------+
1123 | |------>| B=2 |--- | : :
1124 | | +------+ \ | : : +-------+
1125 +-------+ : : \ | +-------+ | |
1126 ---------->| B->2 |------>| |
1127 | +-------+ | CPU 2 |
1131 | | A->0 |------>| 1st |
1133 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1134 barrier causes all effects \ +-------+ | |
1135 prior to the storage of B ---->| A->1 |------>| 2nd |
1136 to be perceptible to CPU 2 +-------+ | |
1140 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1141 before the read barrier completes anyway:
1144 | | +------+ +-------+
1145 | |------>| A=1 |------ --->| A->0 |
1146 | | +------+ \ +-------+
1147 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1148 | | +------+ | +-------+
1149 | |------>| B=2 |--- | : :
1150 | | +------+ \ | : : +-------+
1151 +-------+ : : \ | +-------+ | |
1152 ---------->| B->2 |------>| |
1153 | +-------+ | CPU 2 |
1157 ---->| A->1 |------>| 1st |
1159 rrrrrrrrrrrrrrrrr | |
1161 | A->1 |------>| 2nd |
1166 The guarantee is that the second load will always come up with A == 1 if the
1167 load of B came up with B == 2. No such guarantee exists for the first load of
1168 A; that may come up with either A == 0 or A == 1.
1171 READ MEMORY BARRIERS VS LOAD SPECULATION
1172 ----------------------------------------
1174 Many CPUs speculate with loads: that is they see that they will need to load an
1175 item from memory, and they find a time where they're not using the bus for any
1176 other loads, and so do the load in advance - even though they haven't actually
1177 got to that point in the instruction execution flow yet. This permits the
1178 actual load instruction to potentially complete immediately because the CPU
1179 already has the value to hand.
1181 It may turn out that the CPU didn't actually need the value - perhaps because a
1182 branch circumvented the load - in which case it can discard the value or just
1183 cache it for later use.
1188 ======================= =======================
1190 DIVIDE } Divide instructions generally
1191 DIVIDE } take a long time to perform
1194 Which might appear as this:
1198 --->| B->2 |------>| |
1202 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1203 division speculates on the +-------+ ~ | |
1207 Once the divisions are complete --> : : ~-->| |
1208 the CPU can then perform the : : | |
1209 LOAD with immediate effect : : +-------+
1212 Placing a read barrier or a data dependency barrier just before the second
1216 ======================= =======================
1223 will force any value speculatively obtained to be reconsidered to an extent
1224 dependent on the type of barrier used. If there was no change made to the
1225 speculated memory location, then the speculated value will just be used:
1229 --->| B->2 |------>| |
1233 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1234 division speculates on the +-------+ ~ | |
1239 rrrrrrrrrrrrrrrr~ | |
1246 but if there was an update or an invalidation from another CPU pending, then
1247 the speculation will be cancelled and the value reloaded:
1251 --->| B->2 |------>| |
1255 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1256 division speculates on the +-------+ ~ | |
1261 rrrrrrrrrrrrrrrrr | |
1263 The speculation is discarded ---> --->| A->1 |------>| |
1264 and an updated value is +-------+ | |
1265 retrieved : : +-------+
1271 Transitivity is a deeply intuitive notion about ordering that is not
1272 always provided by real computer systems. The following example
1273 demonstrates transitivity:
1276 ======================= ======================= =======================
1278 STORE X=1 LOAD X STORE Y=1
1279 <general barrier> <general barrier>
1282 Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
1283 This indicates that CPU 2's load from X in some sense follows CPU 1's
1284 store to X and that CPU 2's load from Y in some sense preceded CPU 3's
1285 store to Y. The question is then "Can CPU 3's load from X return 0?"
1287 Because CPU 2's load from X in some sense came after CPU 1's store, it
1288 is natural to expect that CPU 3's load from X must therefore return 1.
1289 This expectation is an example of transitivity: if a load executing on
1290 CPU A follows a load from the same variable executing on CPU B, then
1291 CPU A's load must either return the same value that CPU B's load did,
1292 or must return some later value.
1294 In the Linux kernel, use of general memory barriers guarantees
1295 transitivity. Therefore, in the above example, if CPU 2's load from X
1296 returns 1 and its load from Y returns 0, then CPU 3's load from X must
1299 However, transitivity is -not- guaranteed for read or write barriers.
1300 For example, suppose that CPU 2's general barrier in the above example
1301 is changed to a read barrier as shown below:
1304 ======================= ======================= =======================
1306 STORE X=1 LOAD X STORE Y=1
1307 <read barrier> <general barrier>
1310 This substitution destroys transitivity: in this example, it is perfectly
1311 legal for CPU 2's load from X to return 1, its load from Y to return 0,
1312 and CPU 3's load from X to return 0.
1314 The key point is that although CPU 2's read barrier orders its pair
1315 of loads, it does not guarantee to order CPU 1's store. Therefore, if
1316 this example runs on a system where CPUs 1 and 2 share a store buffer
1317 or a level of cache, CPU 2 might have early access to CPU 1's writes.
1318 General barriers are therefore required to ensure that all CPUs agree
1319 on the combined order of CPU 1's and CPU 2's accesses.
1321 General barriers provide "global transitivity", so that all CPUs will
1322 agree on the order of operations. In contrast, a chain of release-acquire
1323 pairs provides only "local transitivity", so that only those CPUs on
1324 the chain are guaranteed to agree on the combined order of the accesses.
1325 For example, switching to C code in deference to Herman Hollerith:
1331 r0 = smp_load_acquire(&x);
1333 smp_store_release(&y, 1);
1338 r1 = smp_load_acquire(&y);
1341 smp_store_release(&z, 1);
1346 r2 = smp_load_acquire(&z);
1347 smp_store_release(&x, 1);
1357 Because cpu0(), cpu1(), and cpu2() participate in a local transitive
1358 chain of smp_store_release()/smp_load_acquire() pairs, the following
1359 outcome is prohibited:
1361 r0 == 1 && r1 == 1 && r2 == 1
1363 Furthermore, because of the release-acquire relationship between cpu0()
1364 and cpu1(), cpu1() must see cpu0()'s writes, so that the following
1365 outcome is prohibited:
1369 However, the transitivity of release-acquire is local to the participating
1370 CPUs and does not apply to cpu3(). Therefore, the following outcome
1373 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0
1375 As an aside, the following outcome is also possible:
1377 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1
1379 Although cpu0(), cpu1(), and cpu2() will see their respective reads and
1380 writes in order, CPUs not involved in the release-acquire chain might
1381 well disagree on the order. This disagreement stems from the fact that
1382 the weak memory-barrier instructions used to implement smp_load_acquire()
1383 and smp_store_release() are not required to order prior stores against
1384 subsequent loads in all cases. This means that cpu3() can see cpu0()'s
1385 store to u as happening -after- cpu1()'s load from v, even though
1386 both cpu0() and cpu1() agree that these two operations occurred in the
1389 However, please keep in mind that smp_load_acquire() is not magic.
1390 In particular, it simply reads from its argument with ordering. It does
1391 -not- ensure that any particular value will be read. Therefore, the
1392 following outcome is possible:
1394 r0 == 0 && r1 == 0 && r2 == 0 && r5 == 0
1396 Note that this outcome can happen even on a mythical sequentially
1397 consistent system where nothing is ever reordered.
1399 To reiterate, if your code requires global transitivity, use general
1400 barriers throughout.
1403 ========================
1404 EXPLICIT KERNEL BARRIERS
1405 ========================
1407 The Linux kernel has a variety of different barriers that act at different
1410 (*) Compiler barrier.
1412 (*) CPU memory barriers.
1414 (*) MMIO write barrier.
1420 The Linux kernel has an explicit compiler barrier function that prevents the
1421 compiler from moving the memory accesses either side of it to the other side:
1425 This is a general barrier -- there are no read-read or write-write
1426 variants of barrier(). However, READ_ONCE() and WRITE_ONCE() can be
1427 thought of as weak forms of barrier() that affect only the specific
1428 accesses flagged by the READ_ONCE() or WRITE_ONCE().
1430 The barrier() function has the following effects:
1432 (*) Prevents the compiler from reordering accesses following the
1433 barrier() to precede any accesses preceding the barrier().
1434 One example use for this property is to ease communication between
1435 interrupt-handler code and the code that was interrupted.
1437 (*) Within a loop, forces the compiler to load the variables used
1438 in that loop's conditional on each pass through that loop.
1440 The READ_ONCE() and WRITE_ONCE() functions can prevent any number of
1441 optimizations that, while perfectly safe in single-threaded code, can
1442 be fatal in concurrent code. Here are some examples of these sorts
1445 (*) The compiler is within its rights to reorder loads and stores
1446 to the same variable, and in some cases, the CPU is within its
1447 rights to reorder loads to the same variable. This means that
1453 Might result in an older value of x stored in a[1] than in a[0].
1454 Prevent both the compiler and the CPU from doing this as follows:
1456 a[0] = READ_ONCE(x);
1457 a[1] = READ_ONCE(x);
1459 In short, READ_ONCE() and WRITE_ONCE() provide cache coherence for
1460 accesses from multiple CPUs to a single variable.
1462 (*) The compiler is within its rights to merge successive loads from
1463 the same variable. Such merging can cause the compiler to "optimize"
1467 do_something_with(tmp);
1469 into the following code, which, although in some sense legitimate
1470 for single-threaded code, is almost certainly not what the developer
1475 do_something_with(tmp);
1477 Use READ_ONCE() to prevent the compiler from doing this to you:
1479 while (tmp = READ_ONCE(a))
1480 do_something_with(tmp);
1482 (*) The compiler is within its rights to reload a variable, for example,
1483 in cases where high register pressure prevents the compiler from
1484 keeping all data of interest in registers. The compiler might
1485 therefore optimize the variable 'tmp' out of our previous example:
1488 do_something_with(tmp);
1490 This could result in the following code, which is perfectly safe in
1491 single-threaded code, but can be fatal in concurrent code:
1494 do_something_with(a);
1496 For example, the optimized version of this code could result in
1497 passing a zero to do_something_with() in the case where the variable
1498 a was modified by some other CPU between the "while" statement and
1499 the call to do_something_with().
1501 Again, use READ_ONCE() to prevent the compiler from doing this:
1503 while (tmp = READ_ONCE(a))
1504 do_something_with(tmp);
1506 Note that if the compiler runs short of registers, it might save
1507 tmp onto the stack. The overhead of this saving and later restoring
1508 is why compilers reload variables. Doing so is perfectly safe for
1509 single-threaded code, so you need to tell the compiler about cases
1510 where it is not safe.
1512 (*) The compiler is within its rights to omit a load entirely if it knows
1513 what the value will be. For example, if the compiler can prove that
1514 the value of variable 'a' is always zero, it can optimize this code:
1517 do_something_with(tmp);
1523 This transformation is a win for single-threaded code because it
1524 gets rid of a load and a branch. The problem is that the compiler
1525 will carry out its proof assuming that the current CPU is the only
1526 one updating variable 'a'. If variable 'a' is shared, then the
1527 compiler's proof will be erroneous. Use READ_ONCE() to tell the
1528 compiler that it doesn't know as much as it thinks it does:
1530 while (tmp = READ_ONCE(a))
1531 do_something_with(tmp);
1533 But please note that the compiler is also closely watching what you
1534 do with the value after the READ_ONCE(). For example, suppose you
1535 do the following and MAX is a preprocessor macro with the value 1:
1537 while ((tmp = READ_ONCE(a)) % MAX)
1538 do_something_with(tmp);
1540 Then the compiler knows that the result of the "%" operator applied
1541 to MAX will always be zero, again allowing the compiler to optimize
1542 the code into near-nonexistence. (It will still load from the
1545 (*) Similarly, the compiler is within its rights to omit a store entirely
1546 if it knows that the variable already has the value being stored.
1547 Again, the compiler assumes that the current CPU is the only one
1548 storing into the variable, which can cause the compiler to do the
1549 wrong thing for shared variables. For example, suppose you have
1553 ... Code that does not store to variable a ...
1556 The compiler sees that the value of variable 'a' is already zero, so
1557 it might well omit the second store. This would come as a fatal
1558 surprise if some other CPU might have stored to variable 'a' in the
1561 Use WRITE_ONCE() to prevent the compiler from making this sort of
1565 ... Code that does not store to variable a ...
1568 (*) The compiler is within its rights to reorder memory accesses unless
1569 you tell it not to. For example, consider the following interaction
1570 between process-level code and an interrupt handler:
1572 void process_level(void)
1574 msg = get_message();
1578 void interrupt_handler(void)
1581 process_message(msg);
1584 There is nothing to prevent the compiler from transforming
1585 process_level() to the following, in fact, this might well be a
1586 win for single-threaded code:
1588 void process_level(void)
1591 msg = get_message();
1594 If the interrupt occurs between these two statement, then
1595 interrupt_handler() might be passed a garbled msg. Use WRITE_ONCE()
1596 to prevent this as follows:
1598 void process_level(void)
1600 WRITE_ONCE(msg, get_message());
1601 WRITE_ONCE(flag, true);
1604 void interrupt_handler(void)
1606 if (READ_ONCE(flag))
1607 process_message(READ_ONCE(msg));
1610 Note that the READ_ONCE() and WRITE_ONCE() wrappers in
1611 interrupt_handler() are needed if this interrupt handler can itself
1612 be interrupted by something that also accesses 'flag' and 'msg',
1613 for example, a nested interrupt or an NMI. Otherwise, READ_ONCE()
1614 and WRITE_ONCE() are not needed in interrupt_handler() other than
1615 for documentation purposes. (Note also that nested interrupts
1616 do not typically occur in modern Linux kernels, in fact, if an
1617 interrupt handler returns with interrupts enabled, you will get a
1620 You should assume that the compiler can move READ_ONCE() and
1621 WRITE_ONCE() past code not containing READ_ONCE(), WRITE_ONCE(),
1622 barrier(), or similar primitives.
1624 This effect could also be achieved using barrier(), but READ_ONCE()
1625 and WRITE_ONCE() are more selective: With READ_ONCE() and
1626 WRITE_ONCE(), the compiler need only forget the contents of the
1627 indicated memory locations, while with barrier() the compiler must
1628 discard the value of all memory locations that it has currented
1629 cached in any machine registers. Of course, the compiler must also
1630 respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur,
1631 though the CPU of course need not do so.
1633 (*) The compiler is within its rights to invent stores to a variable,
1634 as in the following example:
1641 The compiler might save a branch by optimizing this as follows:
1647 In single-threaded code, this is not only safe, but also saves
1648 a branch. Unfortunately, in concurrent code, this optimization
1649 could cause some other CPU to see a spurious value of 42 -- even
1650 if variable 'a' was never zero -- when loading variable 'b'.
1651 Use WRITE_ONCE() to prevent this as follows:
1658 The compiler can also invent loads. These are usually less
1659 damaging, but they can result in cache-line bouncing and thus in
1660 poor performance and scalability. Use READ_ONCE() to prevent
1663 (*) For aligned memory locations whose size allows them to be accessed
1664 with a single memory-reference instruction, prevents "load tearing"
1665 and "store tearing," in which a single large access is replaced by
1666 multiple smaller accesses. For example, given an architecture having
1667 16-bit store instructions with 7-bit immediate fields, the compiler
1668 might be tempted to use two 16-bit store-immediate instructions to
1669 implement the following 32-bit store:
1673 Please note that GCC really does use this sort of optimization,
1674 which is not surprising given that it would likely take more
1675 than two instructions to build the constant and then store it.
1676 This optimization can therefore be a win in single-threaded code.
1677 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1678 this optimization in a volatile store. In the absence of such bugs,
1679 use of WRITE_ONCE() prevents store tearing in the following example:
1681 WRITE_ONCE(p, 0x00010002);
1683 Use of packed structures can also result in load and store tearing,
1686 struct __attribute__((__packed__)) foo {
1691 struct foo foo1, foo2;
1698 Because there are no READ_ONCE() or WRITE_ONCE() wrappers and no
1699 volatile markings, the compiler would be well within its rights to
1700 implement these three assignment statements as a pair of 32-bit
1701 loads followed by a pair of 32-bit stores. This would result in
1702 load tearing on 'foo1.b' and store tearing on 'foo2.b'. READ_ONCE()
1703 and WRITE_ONCE() again prevent tearing in this example:
1706 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b));
1709 All that aside, it is never necessary to use READ_ONCE() and
1710 WRITE_ONCE() on a variable that has been marked volatile. For example,
1711 because 'jiffies' is marked volatile, it is never necessary to
1712 say READ_ONCE(jiffies). The reason for this is that READ_ONCE() and
1713 WRITE_ONCE() are implemented as volatile casts, which has no effect when
1714 its argument is already marked volatile.
1716 Please note that these compiler barriers have no direct effect on the CPU,
1717 which may then reorder things however it wishes.
1723 The Linux kernel has eight basic CPU memory barriers:
1725 TYPE MANDATORY SMP CONDITIONAL
1726 =============== ======================= ===========================
1727 GENERAL mb() smp_mb()
1728 WRITE wmb() smp_wmb()
1729 READ rmb() smp_rmb()
1730 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1733 All memory barriers except the data dependency barriers imply a compiler
1734 barrier. Data dependencies do not impose any additional compiler ordering.
1736 Aside: In the case of data dependencies, the compiler would be expected
1737 to issue the loads in the correct order (eg. `a[b]` would have to load
1738 the value of b before loading a[b]), however there is no guarantee in
1739 the C specification that the compiler may not speculate the value of b
1740 (eg. is equal to 1) and load a before b (eg. tmp = a[1]; if (b != 1)
1741 tmp = a[b]; ). There is also the problem of a compiler reloading b after
1742 having loaded a[b], thus having a newer copy of b than a[b]. A consensus
1743 has not yet been reached about these problems, however the READ_ONCE()
1744 macro is a good place to start looking.
1746 SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1747 systems because it is assumed that a CPU will appear to be self-consistent,
1748 and will order overlapping accesses correctly with respect to itself.
1749 However, see the subsection on "Virtual Machine Guests" below.
1751 [!] Note that SMP memory barriers _must_ be used to control the ordering of
1752 references to shared memory on SMP systems, though the use of locking instead
1755 Mandatory barriers should not be used to control SMP effects, since mandatory
1756 barriers impose unnecessary overhead on both SMP and UP systems. They may,
1757 however, be used to control MMIO effects on accesses through relaxed memory I/O
1758 windows. These barriers are required even on non-SMP systems as they affect
1759 the order in which memory operations appear to a device by prohibiting both the
1760 compiler and the CPU from reordering them.
1763 There are some more advanced barrier functions:
1765 (*) smp_store_mb(var, value)
1767 This assigns the value to the variable and then inserts a full memory
1768 barrier after it. It isn't guaranteed to insert anything more than a
1769 compiler barrier in a UP compilation.
1772 (*) smp_mb__before_atomic();
1773 (*) smp_mb__after_atomic();
1775 These are for use with atomic (such as add, subtract, increment and
1776 decrement) functions that don't return a value, especially when used for
1777 reference counting. These functions do not imply memory barriers.
1779 These are also used for atomic bitop functions that do not return a
1780 value (such as set_bit and clear_bit).
1782 As an example, consider a piece of code that marks an object as being dead
1783 and then decrements the object's reference count:
1786 smp_mb__before_atomic();
1787 atomic_dec(&obj->ref_count);
1789 This makes sure that the death mark on the object is perceived to be set
1790 *before* the reference counter is decremented.
1792 See Documentation/atomic_ops.txt for more information. See the "Atomic
1793 operations" subsection for information on where to use these.
1796 (*) lockless_dereference();
1797 This can be thought of as a pointer-fetch wrapper around the
1798 smp_read_barrier_depends() data-dependency barrier.
1800 This is also similar to rcu_dereference(), but in cases where
1801 object lifetime is handled by some mechanism other than RCU, for
1802 example, when the objects removed only when the system goes down.
1803 In addition, lockless_dereference() is used in some data structures
1804 that can be used both with and without RCU.
1810 These are for use with consistent memory to guarantee the ordering
1811 of writes or reads of shared memory accessible to both the CPU and a
1814 For example, consider a device driver that shares memory with a device
1815 and uses a descriptor status value to indicate if the descriptor belongs
1816 to the device or the CPU, and a doorbell to notify it when new
1817 descriptors are available:
1819 if (desc->status != DEVICE_OWN) {
1820 /* do not read data until we own descriptor */
1823 /* read/modify data */
1824 read_data = desc->data;
1825 desc->data = write_data;
1827 /* flush modifications before status update */
1830 /* assign ownership */
1831 desc->status = DEVICE_OWN;
1833 /* force memory to sync before notifying device via MMIO */
1836 /* notify device of new descriptors */
1837 writel(DESC_NOTIFY, doorbell);
1840 The dma_rmb() allows us guarantee the device has released ownership
1841 before we read the data from the descriptor, and the dma_wmb() allows
1842 us to guarantee the data is written to the descriptor before the device
1843 can see it now has ownership. The wmb() is needed to guarantee that the
1844 cache coherent memory writes have completed before attempting a write to
1845 the cache incoherent MMIO region.
1847 See Documentation/DMA-API.txt for more information on consistent memory.
1852 The Linux kernel also has a special barrier for use with memory-mapped I/O
1857 This is a variation on the mandatory write barrier that causes writes to weakly
1858 ordered I/O regions to be partially ordered. Its effects may go beyond the
1859 CPU->Hardware interface and actually affect the hardware at some level.
1861 See the subsection "Locks vs I/O accesses" for more information.
1864 ===============================
1865 IMPLICIT KERNEL MEMORY BARRIERS
1866 ===============================
1868 Some of the other functions in the linux kernel imply memory barriers, amongst
1869 which are locking and scheduling functions.
1871 This specification is a _minimum_ guarantee; any particular architecture may
1872 provide more substantial guarantees, but these may not be relied upon outside
1873 of arch specific code.
1879 The Linux kernel has a number of locking constructs:
1887 In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
1888 for each construct. These operations all imply certain barriers:
1890 (1) ACQUIRE operation implication:
1892 Memory operations issued after the ACQUIRE will be completed after the
1893 ACQUIRE operation has completed.
1895 Memory operations issued before the ACQUIRE may be completed after
1896 the ACQUIRE operation has completed. An smp_mb__before_spinlock(),
1897 combined with a following ACQUIRE, orders prior stores against
1898 subsequent loads and stores. Note that this is weaker than smp_mb()!
1899 The smp_mb__before_spinlock() primitive is free on many architectures.
1901 (2) RELEASE operation implication:
1903 Memory operations issued before the RELEASE will be completed before the
1904 RELEASE operation has completed.
1906 Memory operations issued after the RELEASE may be completed before the
1907 RELEASE operation has completed.
1909 (3) ACQUIRE vs ACQUIRE implication:
1911 All ACQUIRE operations issued before another ACQUIRE operation will be
1912 completed before that ACQUIRE operation.
1914 (4) ACQUIRE vs RELEASE implication:
1916 All ACQUIRE operations issued before a RELEASE operation will be
1917 completed before the RELEASE operation.
1919 (5) Failed conditional ACQUIRE implication:
1921 Certain locking variants of the ACQUIRE operation may fail, either due to
1922 being unable to get the lock immediately, or due to receiving an unblocked
1923 signal whilst asleep waiting for the lock to become available. Failed
1924 locks do not imply any sort of barrier.
1926 [!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
1927 one-way barriers is that the effects of instructions outside of a critical
1928 section may seep into the inside of the critical section.
1930 An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
1931 because it is possible for an access preceding the ACQUIRE to happen after the
1932 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
1933 the two accesses can themselves then cross:
1942 ACQUIRE M, STORE *B, STORE *A, RELEASE M
1944 When the ACQUIRE and RELEASE are a lock acquisition and release,
1945 respectively, this same reordering can occur if the lock's ACQUIRE and
1946 RELEASE are to the same lock variable, but only from the perspective of
1947 another CPU not holding that lock. In short, a ACQUIRE followed by an
1948 RELEASE may -not- be assumed to be a full memory barrier.
1950 Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
1951 not imply a full memory barrier. Therefore, the CPU's execution of the
1952 critical sections corresponding to the RELEASE and the ACQUIRE can cross,
1962 ACQUIRE N, STORE *B, STORE *A, RELEASE M
1964 It might appear that this reordering could introduce a deadlock.
1965 However, this cannot happen because if such a deadlock threatened,
1966 the RELEASE would simply complete, thereby avoiding the deadlock.
1970 One key point is that we are only talking about the CPU doing
1971 the reordering, not the compiler. If the compiler (or, for
1972 that matter, the developer) switched the operations, deadlock
1975 But suppose the CPU reordered the operations. In this case,
1976 the unlock precedes the lock in the assembly code. The CPU
1977 simply elected to try executing the later lock operation first.
1978 If there is a deadlock, this lock operation will simply spin (or
1979 try to sleep, but more on that later). The CPU will eventually
1980 execute the unlock operation (which preceded the lock operation
1981 in the assembly code), which will unravel the potential deadlock,
1982 allowing the lock operation to succeed.
1984 But what if the lock is a sleeplock? In that case, the code will
1985 try to enter the scheduler, where it will eventually encounter
1986 a memory barrier, which will force the earlier unlock operation
1987 to complete, again unraveling the deadlock. There might be
1988 a sleep-unlock race, but the locking primitive needs to resolve
1989 such races properly in any case.
1991 Locks and semaphores may not provide any guarantee of ordering on UP compiled
1992 systems, and so cannot be counted on in such a situation to actually achieve
1993 anything at all - especially with respect to I/O accesses - unless combined
1994 with interrupt disabling operations.
1996 See also the section on "Inter-CPU locking barrier effects".
1999 As an example, consider the following:
2010 The following sequence of events is acceptable:
2012 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
2014 [+] Note that {*F,*A} indicates a combined access.
2016 But none of the following are:
2018 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
2019 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
2020 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
2021 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
2025 INTERRUPT DISABLING FUNCTIONS
2026 -----------------------------
2028 Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
2029 (RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
2030 barriers are required in such a situation, they must be provided from some
2034 SLEEP AND WAKE-UP FUNCTIONS
2035 ---------------------------
2037 Sleeping and waking on an event flagged in global data can be viewed as an
2038 interaction between two pieces of data: the task state of the task waiting for
2039 the event and the global data used to indicate the event. To make sure that
2040 these appear to happen in the right order, the primitives to begin the process
2041 of going to sleep, and the primitives to initiate a wake up imply certain
2044 Firstly, the sleeper normally follows something like this sequence of events:
2047 set_current_state(TASK_UNINTERRUPTIBLE);
2048 if (event_indicated)
2053 A general memory barrier is interpolated automatically by set_current_state()
2054 after it has altered the task state:
2057 ===============================
2058 set_current_state();
2060 STORE current->state
2062 LOAD event_indicated
2064 set_current_state() may be wrapped by:
2067 prepare_to_wait_exclusive();
2069 which therefore also imply a general memory barrier after setting the state.
2070 The whole sequence above is available in various canned forms, all of which
2071 interpolate the memory barrier in the right place:
2074 wait_event_interruptible();
2075 wait_event_interruptible_exclusive();
2076 wait_event_interruptible_timeout();
2077 wait_event_killable();
2078 wait_event_timeout();
2083 Secondly, code that performs a wake up normally follows something like this:
2085 event_indicated = 1;
2086 wake_up(&event_wait_queue);
2090 event_indicated = 1;
2091 wake_up_process(event_daemon);
2093 A write memory barrier is implied by wake_up() and co. if and only if they wake
2094 something up. The barrier occurs before the task state is cleared, and so sits
2095 between the STORE to indicate the event and the STORE to set TASK_RUNNING:
2098 =============================== ===============================
2099 set_current_state(); STORE event_indicated
2100 smp_store_mb(); wake_up();
2101 STORE current->state <write barrier>
2102 <general barrier> STORE current->state
2103 LOAD event_indicated
2105 To repeat, this write memory barrier is present if and only if something
2106 is actually awakened. To see this, consider the following sequence of
2107 events, where X and Y are both initially zero:
2110 =============================== ===============================
2111 X = 1; STORE event_indicated
2112 smp_mb(); wake_up();
2113 Y = 1; wait_event(wq, Y == 1);
2114 wake_up(); load from Y sees 1, no memory barrier
2115 load from X might see 0
2117 In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed
2120 The available waker functions include:
2126 wake_up_interruptible();
2127 wake_up_interruptible_all();
2128 wake_up_interruptible_nr();
2129 wake_up_interruptible_poll();
2130 wake_up_interruptible_sync();
2131 wake_up_interruptible_sync_poll();
2133 wake_up_locked_poll();
2139 [!] Note that the memory barriers implied by the sleeper and the waker do _not_
2140 order multiple stores before the wake-up with respect to loads of those stored
2141 values after the sleeper has called set_current_state(). For instance, if the
2144 set_current_state(TASK_INTERRUPTIBLE);
2145 if (event_indicated)
2147 __set_current_state(TASK_RUNNING);
2148 do_something(my_data);
2153 event_indicated = 1;
2154 wake_up(&event_wait_queue);
2156 there's no guarantee that the change to event_indicated will be perceived by
2157 the sleeper as coming after the change to my_data. In such a circumstance, the
2158 code on both sides must interpolate its own memory barriers between the
2159 separate data accesses. Thus the above sleeper ought to do:
2161 set_current_state(TASK_INTERRUPTIBLE);
2162 if (event_indicated) {
2164 do_something(my_data);
2167 and the waker should do:
2171 event_indicated = 1;
2172 wake_up(&event_wait_queue);
2175 MISCELLANEOUS FUNCTIONS
2176 -----------------------
2178 Other functions that imply barriers:
2180 (*) schedule() and similar imply full memory barriers.
2183 ===================================
2184 INTER-CPU ACQUIRING BARRIER EFFECTS
2185 ===================================
2187 On SMP systems locking primitives give a more substantial form of barrier: one
2188 that does affect memory access ordering on other CPUs, within the context of
2189 conflict on any particular lock.
2192 ACQUIRES VS MEMORY ACCESSES
2193 ---------------------------
2195 Consider the following: the system has a pair of spinlocks (M) and (Q), and
2196 three CPUs; then should the following sequence of events occur:
2199 =============================== ===============================
2200 WRITE_ONCE(*A, a); WRITE_ONCE(*E, e);
2202 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);
2203 WRITE_ONCE(*C, c); WRITE_ONCE(*G, g);
2205 WRITE_ONCE(*D, d); WRITE_ONCE(*H, h);
2207 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2208 through *H occur in, other than the constraints imposed by the separate locks
2209 on the separate CPUs. It might, for example, see:
2211 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2213 But it won't see any of:
2215 *B, *C or *D preceding ACQUIRE M
2216 *A, *B or *C following RELEASE M
2217 *F, *G or *H preceding ACQUIRE Q
2218 *E, *F or *G following RELEASE Q
2222 ACQUIRES VS I/O ACCESSES
2223 ------------------------
2225 Under certain circumstances (especially involving NUMA), I/O accesses within
2226 two spinlocked sections on two different CPUs may be seen as interleaved by the
2227 PCI bridge, because the PCI bridge does not necessarily participate in the
2228 cache-coherence protocol, and is therefore incapable of issuing the required
2229 read memory barriers.
2234 =============================== ===============================
2244 may be seen by the PCI bridge as follows:
2246 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
2248 which would probably cause the hardware to malfunction.
2251 What is necessary here is to intervene with an mmiowb() before dropping the
2252 spinlock, for example:
2255 =============================== ===============================
2267 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2268 before either of the stores issued on CPU 2.
2271 Furthermore, following a store by a load from the same device obviates the need
2272 for the mmiowb(), because the load forces the store to complete before the load
2276 =============================== ===============================
2287 See Documentation/DocBook/deviceiobook.tmpl for more information.
2290 =================================
2291 WHERE ARE MEMORY BARRIERS NEEDED?
2292 =================================
2294 Under normal operation, memory operation reordering is generally not going to
2295 be a problem as a single-threaded linear piece of code will still appear to
2296 work correctly, even if it's in an SMP kernel. There are, however, four
2297 circumstances in which reordering definitely _could_ be a problem:
2299 (*) Interprocessor interaction.
2301 (*) Atomic operations.
2303 (*) Accessing devices.
2308 INTERPROCESSOR INTERACTION
2309 --------------------------
2311 When there's a system with more than one processor, more than one CPU in the
2312 system may be working on the same data set at the same time. This can cause
2313 synchronisation problems, and the usual way of dealing with them is to use
2314 locks. Locks, however, are quite expensive, and so it may be preferable to
2315 operate without the use of a lock if at all possible. In such a case
2316 operations that affect both CPUs may have to be carefully ordered to prevent
2319 Consider, for example, the R/W semaphore slow path. Here a waiting process is
2320 queued on the semaphore, by virtue of it having a piece of its stack linked to
2321 the semaphore's list of waiting processes:
2323 struct rw_semaphore {
2326 struct list_head waiters;
2329 struct rwsem_waiter {
2330 struct list_head list;
2331 struct task_struct *task;
2334 To wake up a particular waiter, the up_read() or up_write() functions have to:
2336 (1) read the next pointer from this waiter's record to know as to where the
2337 next waiter record is;
2339 (2) read the pointer to the waiter's task structure;
2341 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2343 (4) call wake_up_process() on the task; and
2345 (5) release the reference held on the waiter's task struct.
2347 In other words, it has to perform this sequence of events:
2349 LOAD waiter->list.next;
2355 and if any of these steps occur out of order, then the whole thing may
2358 Once it has queued itself and dropped the semaphore lock, the waiter does not
2359 get the lock again; it instead just waits for its task pointer to be cleared
2360 before proceeding. Since the record is on the waiter's stack, this means that
2361 if the task pointer is cleared _before_ the next pointer in the list is read,
2362 another CPU might start processing the waiter and might clobber the waiter's
2363 stack before the up*() function has a chance to read the next pointer.
2365 Consider then what might happen to the above sequence of events:
2368 =============================== ===============================
2375 Woken up by other event
2380 foo() clobbers *waiter
2382 LOAD waiter->list.next;
2385 This could be dealt with using the semaphore lock, but then the down_xxx()
2386 function has to needlessly get the spinlock again after being woken up.
2388 The way to deal with this is to insert a general SMP memory barrier:
2390 LOAD waiter->list.next;
2397 In this case, the barrier makes a guarantee that all memory accesses before the
2398 barrier will appear to happen before all the memory accesses after the barrier
2399 with respect to the other CPUs on the system. It does _not_ guarantee that all
2400 the memory accesses before the barrier will be complete by the time the barrier
2401 instruction itself is complete.
2403 On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2404 compiler barrier, thus making sure the compiler emits the instructions in the
2405 right order without actually intervening in the CPU. Since there's only one
2406 CPU, that CPU's dependency ordering logic will take care of everything else.
2412 Whilst they are technically interprocessor interaction considerations, atomic
2413 operations are noted specially as some of them imply full memory barriers and
2414 some don't, but they're very heavily relied on as a group throughout the
2417 Any atomic operation that modifies some state in memory and returns information
2418 about the state (old or new) implies an SMP-conditional general memory barrier
2419 (smp_mb()) on each side of the actual operation (with the exception of
2420 explicit lock operations, described later). These include:
2423 atomic_xchg(); atomic_long_xchg();
2424 atomic_inc_return(); atomic_long_inc_return();
2425 atomic_dec_return(); atomic_long_dec_return();
2426 atomic_add_return(); atomic_long_add_return();
2427 atomic_sub_return(); atomic_long_sub_return();
2428 atomic_inc_and_test(); atomic_long_inc_and_test();
2429 atomic_dec_and_test(); atomic_long_dec_and_test();
2430 atomic_sub_and_test(); atomic_long_sub_and_test();
2431 atomic_add_negative(); atomic_long_add_negative();
2433 test_and_clear_bit();
2434 test_and_change_bit();
2438 atomic_cmpxchg(); atomic_long_cmpxchg();
2439 atomic_add_unless(); atomic_long_add_unless();
2441 These are used for such things as implementing ACQUIRE-class and RELEASE-class
2442 operations and adjusting reference counters towards object destruction, and as
2443 such the implicit memory barrier effects are necessary.
2446 The following operations are potential problems as they do _not_ imply memory
2447 barriers, but might be used for implementing such things as RELEASE-class
2455 With these the appropriate explicit memory barrier should be used if necessary
2456 (smp_mb__before_atomic() for instance).
2459 The following also do _not_ imply memory barriers, and so may require explicit
2460 memory barriers under some circumstances (smp_mb__before_atomic() for
2468 If they're used for statistics generation, then they probably don't need memory
2469 barriers, unless there's a coupling between statistical data.
2471 If they're used for reference counting on an object to control its lifetime,
2472 they probably don't need memory barriers because either the reference count
2473 will be adjusted inside a locked section, or the caller will already hold
2474 sufficient references to make the lock, and thus a memory barrier unnecessary.
2476 If they're used for constructing a lock of some description, then they probably
2477 do need memory barriers as a lock primitive generally has to do things in a
2480 Basically, each usage case has to be carefully considered as to whether memory
2481 barriers are needed or not.
2483 The following operations are special locking primitives:
2485 test_and_set_bit_lock();
2487 __clear_bit_unlock();
2489 These implement ACQUIRE-class and RELEASE-class operations. These should be used in
2490 preference to other operations when implementing locking primitives, because
2491 their implementations can be optimised on many architectures.
2493 [!] Note that special memory barrier primitives are available for these
2494 situations because on some CPUs the atomic instructions used imply full memory
2495 barriers, and so barrier instructions are superfluous in conjunction with them,
2496 and in such cases the special barrier primitives will be no-ops.
2498 See Documentation/atomic_ops.txt for more information.
2504 Many devices can be memory mapped, and so appear to the CPU as if they're just
2505 a set of memory locations. To control such a device, the driver usually has to
2506 make the right memory accesses in exactly the right order.
2508 However, having a clever CPU or a clever compiler creates a potential problem
2509 in that the carefully sequenced accesses in the driver code won't reach the
2510 device in the requisite order if the CPU or the compiler thinks it is more
2511 efficient to reorder, combine or merge accesses - something that would cause
2512 the device to malfunction.
2514 Inside of the Linux kernel, I/O should be done through the appropriate accessor
2515 routines - such as inb() or writel() - which know how to make such accesses
2516 appropriately sequential. Whilst this, for the most part, renders the explicit
2517 use of memory barriers unnecessary, there are a couple of situations where they
2520 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
2521 so for _all_ general drivers locks should be used and mmiowb() must be
2522 issued prior to unlocking the critical section.
2524 (2) If the accessor functions are used to refer to an I/O memory window with
2525 relaxed memory access properties, then _mandatory_ memory barriers are
2526 required to enforce ordering.
2528 See Documentation/DocBook/deviceiobook.tmpl for more information.
2534 A driver may be interrupted by its own interrupt service routine, and thus the
2535 two parts of the driver may interfere with each other's attempts to control or
2538 This may be alleviated - at least in part - by disabling local interrupts (a
2539 form of locking), such that the critical operations are all contained within
2540 the interrupt-disabled section in the driver. Whilst the driver's interrupt
2541 routine is executing, the driver's core may not run on the same CPU, and its
2542 interrupt is not permitted to happen again until the current interrupt has been
2543 handled, thus the interrupt handler does not need to lock against that.
2545 However, consider a driver that was talking to an ethernet card that sports an
2546 address register and a data register. If that driver's core talks to the card
2547 under interrupt-disablement and then the driver's interrupt handler is invoked:
2558 The store to the data register might happen after the second store to the
2559 address register if ordering rules are sufficiently relaxed:
2561 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2564 If ordering rules are relaxed, it must be assumed that accesses done inside an
2565 interrupt disabled section may leak outside of it and may interleave with
2566 accesses performed in an interrupt - and vice versa - unless implicit or
2567 explicit barriers are used.
2569 Normally this won't be a problem because the I/O accesses done inside such
2570 sections will include synchronous load operations on strictly ordered I/O
2571 registers that form implicit I/O barriers. If this isn't sufficient then an
2572 mmiowb() may need to be used explicitly.
2575 A similar situation may occur between an interrupt routine and two routines
2576 running on separate CPUs that communicate with each other. If such a case is
2577 likely, then interrupt-disabling locks should be used to guarantee ordering.
2580 ==========================
2581 KERNEL I/O BARRIER EFFECTS
2582 ==========================
2584 When accessing I/O memory, drivers should use the appropriate accessor
2589 These are intended to talk to I/O space rather than memory space, but
2590 that's primarily a CPU-specific concept. The i386 and x86_64 processors do
2591 indeed have special I/O space access cycles and instructions, but many
2592 CPUs don't have such a concept.
2594 The PCI bus, amongst others, defines an I/O space concept which - on such
2595 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
2596 space. However, it may also be mapped as a virtual I/O space in the CPU's
2597 memory map, particularly on those CPUs that don't support alternate I/O
2600 Accesses to this space may be fully synchronous (as on i386), but
2601 intermediary bridges (such as the PCI host bridge) may not fully honour
2604 They are guaranteed to be fully ordered with respect to each other.
2606 They are not guaranteed to be fully ordered with respect to other types of
2607 memory and I/O operation.
2609 (*) readX(), writeX():
2611 Whether these are guaranteed to be fully ordered and uncombined with
2612 respect to each other on the issuing CPU depends on the characteristics
2613 defined for the memory window through which they're accessing. On later
2614 i386 architecture machines, for example, this is controlled by way of the
2617 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
2618 provided they're not accessing a prefetchable device.
2620 However, intermediary hardware (such as a PCI bridge) may indulge in
2621 deferral if it so wishes; to flush a store, a load from the same location
2622 is preferred[*], but a load from the same device or from configuration
2623 space should suffice for PCI.
2625 [*] NOTE! attempting to load from the same location as was written to may
2626 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2629 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2630 force stores to be ordered.
2632 Please refer to the PCI specification for more information on interactions
2633 between PCI transactions.
2635 (*) readX_relaxed(), writeX_relaxed()
2637 These are similar to readX() and writeX(), but provide weaker memory
2638 ordering guarantees. Specifically, they do not guarantee ordering with
2639 respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee
2640 ordering with respect to LOCK or UNLOCK operations. If the latter is
2641 required, an mmiowb() barrier can be used. Note that relaxed accesses to
2642 the same peripheral are guaranteed to be ordered with respect to each
2645 (*) ioreadX(), iowriteX()
2647 These will perform appropriately for the type of access they're actually
2648 doing, be it inX()/outX() or readX()/writeX().
2651 ========================================
2652 ASSUMED MINIMUM EXECUTION ORDERING MODEL
2653 ========================================
2655 It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2656 maintain the appearance of program causality with respect to itself. Some CPUs
2657 (such as i386 or x86_64) are more constrained than others (such as powerpc or
2658 frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2659 of arch-specific code.
2661 This means that it must be considered that the CPU will execute its instruction
2662 stream in any order it feels like - or even in parallel - provided that if an
2663 instruction in the stream depends on an earlier instruction, then that
2664 earlier instruction must be sufficiently complete[*] before the later
2665 instruction may proceed; in other words: provided that the appearance of
2666 causality is maintained.
2668 [*] Some instructions have more than one effect - such as changing the
2669 condition codes, changing registers or changing memory - and different
2670 instructions may depend on different effects.
2672 A CPU may also discard any instruction sequence that winds up having no
2673 ultimate effect. For example, if two adjacent instructions both load an
2674 immediate value into the same register, the first may be discarded.
2677 Similarly, it has to be assumed that compiler might reorder the instruction
2678 stream in any way it sees fit, again provided the appearance of causality is
2682 ============================
2683 THE EFFECTS OF THE CPU CACHE
2684 ============================
2686 The way cached memory operations are perceived across the system is affected to
2687 a certain extent by the caches that lie between CPUs and memory, and by the
2688 memory coherence system that maintains the consistency of state in the system.
2690 As far as the way a CPU interacts with another part of the system through the
2691 caches goes, the memory system has to include the CPU's caches, and memory
2692 barriers for the most part act at the interface between the CPU and its cache
2693 (memory barriers logically act on the dotted line in the following diagram):
2695 <--- CPU ---> : <----------- Memory ----------->
2697 +--------+ +--------+ : +--------+ +-----------+
2698 | | | | : | | | | +--------+
2699 | CPU | | Memory | : | CPU | | | | |
2700 | Core |--->| Access |----->| Cache |<-->| | | |
2701 | | | Queue | : | | | |--->| Memory |
2702 | | | | : | | | | | |
2703 +--------+ +--------+ : +--------+ | | | |
2704 : | Cache | +--------+
2706 : | Mechanism | +--------+
2707 +--------+ +--------+ : +--------+ | | | |
2708 | | | | : | | | | | |
2709 | CPU | | Memory | : | CPU | | |--->| Device |
2710 | Core |--->| Access |----->| Cache |<-->| | | |
2711 | | | Queue | : | | | | | |
2712 | | | | : | | | | +--------+
2713 +--------+ +--------+ : +--------+ +-----------+
2717 Although any particular load or store may not actually appear outside of the
2718 CPU that issued it since it may have been satisfied within the CPU's own cache,
2719 it will still appear as if the full memory access had taken place as far as the
2720 other CPUs are concerned since the cache coherency mechanisms will migrate the
2721 cacheline over to the accessing CPU and propagate the effects upon conflict.
2723 The CPU core may execute instructions in any order it deems fit, provided the
2724 expected program causality appears to be maintained. Some of the instructions
2725 generate load and store operations which then go into the queue of memory
2726 accesses to be performed. The core may place these in the queue in any order
2727 it wishes, and continue execution until it is forced to wait for an instruction
2730 What memory barriers are concerned with is controlling the order in which
2731 accesses cross from the CPU side of things to the memory side of things, and
2732 the order in which the effects are perceived to happen by the other observers
2735 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2736 their own loads and stores as if they had happened in program order.
2738 [!] MMIO or other device accesses may bypass the cache system. This depends on
2739 the properties of the memory window through which devices are accessed and/or
2740 the use of any special device communication instructions the CPU may have.
2746 Life isn't quite as simple as it may appear above, however: for while the
2747 caches are expected to be coherent, there's no guarantee that that coherency
2748 will be ordered. This means that whilst changes made on one CPU will
2749 eventually become visible on all CPUs, there's no guarantee that they will
2750 become apparent in the same order on those other CPUs.
2753 Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2754 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2759 +--------+ : +--->| Cache A |<------->| |
2760 | | : | +---------+ | |
2762 | | : | +---------+ | |
2763 +--------+ : +--->| Cache B |<------->| |
2766 : +---------+ | System |
2767 +--------+ : +--->| Cache C |<------->| |
2768 | | : | +---------+ | |
2770 | | : | +---------+ | |
2771 +--------+ : +--->| Cache D |<------->| |
2776 Imagine the system has the following properties:
2778 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2781 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2784 (*) whilst the CPU core is interrogating one cache, the other cache may be
2785 making use of the bus to access the rest of the system - perhaps to
2786 displace a dirty cacheline or to do a speculative load;
2788 (*) each cache has a queue of operations that need to be applied to that cache
2789 to maintain coherency with the rest of the system;
2791 (*) the coherency queue is not flushed by normal loads to lines already
2792 present in the cache, even though the contents of the queue may
2793 potentially affect those loads.
2795 Imagine, then, that two writes are made on the first CPU, with a write barrier
2796 between them to guarantee that they will appear to reach that CPU's caches in
2797 the requisite order:
2800 =============== =============== =======================================
2801 u == 0, v == 1 and p == &u, q == &u
2803 smp_wmb(); Make sure change to v is visible before
2805 <A:modify v=2> v is now in cache A exclusively
2807 <B:modify p=&v> p is now in cache B exclusively
2809 The write memory barrier forces the other CPUs in the system to perceive that
2810 the local CPU's caches have apparently been updated in the correct order. But
2811 now imagine that the second CPU wants to read those values:
2814 =============== =============== =======================================
2819 The above pair of reads may then fail to happen in the expected order, as the
2820 cacheline holding p may get updated in one of the second CPU's caches whilst
2821 the update to the cacheline holding v is delayed in the other of the second
2822 CPU's caches by some other cache event:
2825 =============== =============== =======================================
2826 u == 0, v == 1 and p == &u, q == &u
2829 <A:modify v=2> <C:busy>
2833 <B:modify p=&v> <D:commit p=&v>
2836 <C:read *q> Reads from v before v updated in cache
2840 Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
2841 no guarantee that, without intervention, the order of update will be the same
2842 as that committed on CPU 1.
2845 To intervene, we need to interpolate a data dependency barrier or a read
2846 barrier between the loads. This will force the cache to commit its coherency
2847 queue before processing any further requests:
2850 =============== =============== =======================================
2851 u == 0, v == 1 and p == &u, q == &u
2854 <A:modify v=2> <C:busy>
2858 <B:modify p=&v> <D:commit p=&v>
2860 smp_read_barrier_depends()
2864 <C:read *q> Reads from v after v updated in cache
2867 This sort of problem can be encountered on DEC Alpha processors as they have a
2868 split cache that improves performance by making better use of the data bus.
2869 Whilst most CPUs do imply a data dependency barrier on the read when a memory
2870 access depends on a read, not all do, so it may not be relied on.
2872 Other CPUs may also have split caches, but must coordinate between the various
2873 cachelets for normal memory accesses. The semantics of the Alpha removes the
2874 need for coordination in the absence of memory barriers.
2877 CACHE COHERENCY VS DMA
2878 ----------------------
2880 Not all systems maintain cache coherency with respect to devices doing DMA. In
2881 such cases, a device attempting DMA may obtain stale data from RAM because
2882 dirty cache lines may be resident in the caches of various CPUs, and may not
2883 have been written back to RAM yet. To deal with this, the appropriate part of
2884 the kernel must flush the overlapping bits of cache on each CPU (and maybe
2885 invalidate them as well).
2887 In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2888 cache lines being written back to RAM from a CPU's cache after the device has
2889 installed its own data, or cache lines present in the CPU's cache may simply
2890 obscure the fact that RAM has been updated, until at such time as the cacheline
2891 is discarded from the CPU's cache and reloaded. To deal with this, the
2892 appropriate part of the kernel must invalidate the overlapping bits of the
2895 See Documentation/cachetlb.txt for more information on cache management.
2898 CACHE COHERENCY VS MMIO
2899 -----------------------
2901 Memory mapped I/O usually takes place through memory locations that are part of
2902 a window in the CPU's memory space that has different properties assigned than
2903 the usual RAM directed window.
2905 Amongst these properties is usually the fact that such accesses bypass the
2906 caching entirely and go directly to the device buses. This means MMIO accesses
2907 may, in effect, overtake accesses to cached memory that were emitted earlier.
2908 A memory barrier isn't sufficient in such a case, but rather the cache must be
2909 flushed between the cached memory write and the MMIO access if the two are in
2913 =========================
2914 THE THINGS CPUS GET UP TO
2915 =========================
2917 A programmer might take it for granted that the CPU will perform memory
2918 operations in exactly the order specified, so that if the CPU is, for example,
2919 given the following piece of code to execute:
2927 they would then expect that the CPU will complete the memory operation for each
2928 instruction before moving on to the next one, leading to a definite sequence of
2929 operations as seen by external observers in the system:
2931 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2934 Reality is, of course, much messier. With many CPUs and compilers, the above
2935 assumption doesn't hold because:
2937 (*) loads are more likely to need to be completed immediately to permit
2938 execution progress, whereas stores can often be deferred without a
2941 (*) loads may be done speculatively, and the result discarded should it prove
2942 to have been unnecessary;
2944 (*) loads may be done speculatively, leading to the result having been fetched
2945 at the wrong time in the expected sequence of events;
2947 (*) the order of the memory accesses may be rearranged to promote better use
2948 of the CPU buses and caches;
2950 (*) loads and stores may be combined to improve performance when talking to
2951 memory or I/O hardware that can do batched accesses of adjacent locations,
2952 thus cutting down on transaction setup costs (memory and PCI devices may
2953 both be able to do this); and
2955 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2956 mechanisms may alleviate this - once the store has actually hit the cache
2957 - there's no guarantee that the coherency management will be propagated in
2958 order to other CPUs.
2960 So what another CPU, say, might actually observe from the above piece of code
2963 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2965 (Where "LOAD {*C,*D}" is a combined load)
2968 However, it is guaranteed that a CPU will be self-consistent: it will see its
2969 _own_ accesses appear to be correctly ordered, without the need for a memory
2970 barrier. For instance with the following code:
2979 and assuming no intervention by an external influence, it can be assumed that
2980 the final result will appear to be:
2982 U == the original value of *A
2987 The code above may cause the CPU to generate the full sequence of memory
2990 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2992 in that order, but, without intervention, the sequence may have almost any
2993 combination of elements combined or discarded, provided the program's view
2994 of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE()
2995 are -not- optional in the above example, as there are architectures
2996 where a given CPU might reorder successive loads to the same location.
2997 On such architectures, READ_ONCE() and WRITE_ONCE() do whatever is
2998 necessary to prevent this, for example, on Itanium the volatile casts
2999 used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq
3000 and st.rel instructions (respectively) that prevent such reordering.
3002 The compiler may also combine, discard or defer elements of the sequence before
3003 the CPU even sees them.
3014 since, without either a write barrier or an WRITE_ONCE(), it can be
3015 assumed that the effect of the storage of V to *A is lost. Similarly:
3020 may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be
3026 and the LOAD operation never appear outside of the CPU.
3029 AND THEN THERE'S THE ALPHA
3030 --------------------------
3032 The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
3033 some versions of the Alpha CPU have a split data cache, permitting them to have
3034 two semantically-related cache lines updated at separate times. This is where
3035 the data dependency barrier really becomes necessary as this synchronises both
3036 caches with the memory coherence system, thus making it seem like pointer
3037 changes vs new data occur in the right order.
3039 The Alpha defines the Linux kernel's memory barrier model.
3041 See the subsection on "Cache Coherency" above.
3043 VIRTUAL MACHINE GUESTS
3046 Guests running within virtual machines might be affected by SMP effects even if
3047 the guest itself is compiled without SMP support. This is an artifact of
3048 interfacing with an SMP host while running an UP kernel. Using mandatory
3049 barriers for this use-case would be possible but is often suboptimal.
3051 To handle this case optimally, low-level virt_mb() etc macros are available.
3052 These have the same effect as smp_mb() etc when SMP is enabled, but generate
3053 identical code for SMP and non-SMP systems. For example, virtual machine guests
3054 should use virt_mb() rather than smp_mb() when synchronizing against a
3055 (possibly SMP) host.
3057 These are equivalent to smp_mb() etc counterparts in all other respects,
3058 in particular, they do not control MMIO effects: to control
3059 MMIO effects, use mandatory barriers.
3068 Memory barriers can be used to implement circular buffering without the need
3069 of a lock to serialise the producer with the consumer. See:
3071 Documentation/circular-buffers.txt
3080 Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
3082 Chapter 5.2: Physical Address Space Characteristics
3083 Chapter 5.4: Caches and Write Buffers
3084 Chapter 5.5: Data Sharing
3085 Chapter 5.6: Read/Write Ordering
3087 AMD64 Architecture Programmer's Manual Volume 2: System Programming
3088 Chapter 7.1: Memory-Access Ordering
3089 Chapter 7.4: Buffering and Combining Memory Writes
3091 IA-32 Intel Architecture Software Developer's Manual, Volume 3:
3092 System Programming Guide
3093 Chapter 7.1: Locked Atomic Operations
3094 Chapter 7.2: Memory Ordering
3095 Chapter 7.4: Serializing Instructions
3097 The SPARC Architecture Manual, Version 9
3098 Chapter 8: Memory Models
3099 Appendix D: Formal Specification of the Memory Models
3100 Appendix J: Programming with the Memory Models
3102 UltraSPARC Programmer Reference Manual
3103 Chapter 5: Memory Accesses and Cacheability
3104 Chapter 15: Sparc-V9 Memory Models
3106 UltraSPARC III Cu User's Manual
3107 Chapter 9: Memory Models
3109 UltraSPARC IIIi Processor User's Manual
3110 Chapter 8: Memory Models
3112 UltraSPARC Architecture 2005
3114 Appendix D: Formal Specifications of the Memory Models
3116 UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
3117 Chapter 8: Memory Models
3118 Appendix F: Caches and Cache Coherency
3120 Solaris Internals, Core Kernel Architecture, p63-68:
3121 Chapter 3.3: Hardware Considerations for Locks and
3124 Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
3125 for Kernel Programmers:
3126 Chapter 13: Other Memory Models
3128 Intel Itanium Architecture Software Developer's Manual: Volume 1:
3129 Section 2.6: Speculation
3130 Section 4.4: Memory Access
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