Documentation/devicetree/bindings/sound/rockchip-i2s.txt

   1 * Rockchip I2S controller
   2
   3 The I2S bus (Inter-IC sound bus) is a serial link for digital
   4 audio data transfer between devices in the system.
   5
   6 Required properties:
   7
   8 - compatible: should be one of the following:
   9    - "rockchip,rk3066-i2s": for rk3066
  10    - "rockchip,rk3188-i2s", "rockchip,rk3066-i2s": for rk3188
  11    - "rockchip,rk3288-i2s", "rockchip,rk3066-i2s": for rk3288
  12    - "rockchip,rk3368-i2s", "rockchip,rk3066-i2s": for rk3368
  13    - "rockchip,rk3399-i2s", "rockchip,rk3066-i2s": for rk3399
  14 - reg: physical base address of the controller and length of memory mapped
  15   region.
  16 - interrupts: should contain the I2S interrupt.
  17 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
  18         Documentation/devicetree/bindings/dma/dma.txt
  19 - dma-names: should include "tx" and "rx".
  20 - clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
  21 - clock-names: should contain the following:
  22    - "i2s_hclk": clock for I2S BUS
  23    - "i2s_clk" : clock for I2S controller
  24 - rockchip,playback-channels: max playback channels, if not set, 8 channels default.
  25 - rockchip,capture-channels: max capture channels, if not set, 2 channels default.
  26
  27 Required properties for controller which support multi channels
  28 playback/capture:
  29
  30 - rockchip,grf: the phandle of the syscon node for GRF register.
  31
  32 Example for rk3288 I2S controller:
  33
  34 i2s@ff890000 {
  35         compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
  36         reg = <0xff890000 0x10000>;
  37         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  38         dmas = <&pdma1 0>, <&pdma1 1>;
  39         dma-names = "tx", "rx";
  40         clock-names = "i2s_hclk", "i2s_clk";
  41         clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
  42         rockchip,playback-channels = <8>;
  43         rockchip,capture-channels = <2>;
  44 };