1 * UART (Universal Asynchronous Receiver/Transmitter)
11 - For Tegra20, must contain "nvidia,tegra20-uart"
12 - For other Tegra, must contain '"nvidia,<chip>-uart",
13 "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
14 tegra132, or tegra210.
16 - "ralink,rt2880-uart"
19 - "altr,16550-FIFO128"
23 - "serial" if the port type is unknown.
24 - reg : offset and length of the register set for the device.
25 - interrupts : should contain uart interrupt.
26 - clock-frequency : the input clock frequency for the UART
28 clocks phandle to refer to the clk used as per Documentation/devicetree
29 /bindings/clock/clock-bindings.txt
32 - current-speed : the current active speed of the UART.
33 - reg-offset : offset to apply to the mapbase from the start of the registers.
34 - reg-shift : quantity to shift the register offsets by.
35 - reg-io-width : the size (in bytes) of the IO accesses that should be
36 performed on the device. There are some systems that require 32-bit
37 accesses to the UART (e.g. TI davinci).
38 - used-by-rtas : set to indicate that the port is in use by the OpenFirmware
39 RTAS and should not be registered.
40 - no-loopback-test: set to indicate that the port does not implements loopback
42 - fifo-size: the fifo size of the UART.
43 - auto-flow-control: one way to enable automatic flow control support. The
44 driver is allowed to detect support for the capability even without this
46 - tx-threshold: Specify the TX FIFO low water indication for parts with
47 programmable TX FIFO thresholds.
52 Freescale DUART is very similar to the PC16552D (and to a
53 pair of NS16550A), albeit with some nonstandard behavior such as
54 erratum A-004737 (relating to incorrect BRK handling).
56 Represents a single port that is compatible with the DUART found
57 on many Freescale chips (examples include mpc8349, mpc8548,
58 mpc8641d, p4080 and ls2085a).
63 compatible = "ns8250";
64 reg = <0x80230000 0x100>;
65 clock-frequency = <3686400>;