1 * UART (Universal Asynchronous Receiver/Transmitter)
11 - For Tegra20, must contain "nvidia,tegra20-uart"
12 - For other Tegra, must contain '"nvidia,<chip>-uart",
13 "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
14 tegra132, or tegra210.
16 - "ralink,rt2880-uart"
17 - For MediaTek BTIF, must contain '"mediatek,<chip>-btif",
18 "mediatek,mtk-btif"' where <chip> is mt7622, mt7623.
21 - "altr,16550-FIFO128"
26 - "aspeed,ast2400-vuart"
27 - "aspeed,ast2500-vuart"
28 - "nuvoton,npcm750-uart"
29 - "serial" if the port type is unknown.
30 - reg : offset and length of the register set for the device.
31 - interrupts : should contain uart interrupt.
32 - clock-frequency : the input clock frequency for the UART
34 clocks phandle to refer to the clk used as per Documentation/devicetree
35 /bindings/clock/clock-bindings.txt
38 - current-speed : the current active speed of the UART.
39 - reg-offset : offset to apply to the mapbase from the start of the registers.
40 - reg-shift : quantity to shift the register offsets by.
41 - reg-io-width : the size (in bytes) of the IO accesses that should be
42 performed on the device. There are some systems that require 32-bit
43 accesses to the UART (e.g. TI davinci).
44 - used-by-rtas : set to indicate that the port is in use by the OpenFirmware
45 RTAS and should not be registered.
46 - no-loopback-test: set to indicate that the port does not implements loopback
48 - fifo-size: the fifo size of the UART.
49 - auto-flow-control: one way to enable automatic flow control support. The
50 driver is allowed to detect support for the capability even without this
52 - tx-threshold: Specify the TX FIFO low water indication for parts with
53 programmable TX FIFO thresholds.
54 - resets : phandle + reset specifier pairs
55 - overrun-throttle-ms : how long to pause uart rx when input overrun is encountered.
60 Freescale DUART is very similar to the PC16552D (and to a
61 pair of NS16550A), albeit with some nonstandard behavior such as
62 erratum A-004737 (relating to incorrect BRK handling).
64 Represents a single port that is compatible with the DUART found
65 on many Freescale chips (examples include mpc8349, mpc8548,
66 mpc8641d, p4080 and ls2085a).
71 compatible = "ns8250";
72 reg = <0x80230000 0x100>;
73 clock-frequency = <3686400>;