Documentation/devicetree/bindings/riscv/cpus.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: RISC-V bindings for 'cpus' DT nodes
   8
   9 maintainers:
  10   - Paul Walmsley <paul.walmsley@sifive.com>
  11   - Palmer Dabbelt <palmer@sifive.com>
  12
  13 properties:
  14   compatible:
  15     items:
  16       - enum:
  17           - sifive,rocket0
  18           - sifive,e5
  19           - sifive,e51
  20           - sifive,u54-mc
  21           - sifive,u54
  22           - sifive,u5
  23       - const: riscv
  24     description:
  25       Identifies that the hart uses the RISC-V instruction set
  26       and identifies the type of the hart.
  27
  28   mmu-type:
  29     allOf:
  30       - $ref: "/schemas/types.yaml#/definitions/string"
  31       - enum:
  32           - riscv,sv32
  33           - riscv,sv39
  34           - riscv,sv48
  35     description:
  36       Identifies the MMU address translation mode used on this
  37       hart.  These values originate from the RISC-V Privileged
  38       Specification document, available from
  39       https://riscv.org/specifications/
  40
  41   riscv,isa:
  42     allOf:
  43       - $ref: "/schemas/types.yaml#/definitions/string"
  44       - enum:
  45           - rv64imac
  46           - rv64imafdc
  47     description:
  48       Identifies the specific RISC-V instruction set architecture
  49       supported by the hart.  These are documented in the RISC-V
  50       User-Level ISA document, available from
  51       https://riscv.org/specifications/
  52
  53   timebase-frequency:
  54     type: integer
  55     minimum: 1
  56     description:
  57       Specifies the clock frequency of the system timer in Hz.
  58       This value is common to all harts on a single system image.
  59
  60   interrupt-controller:
  61     type: object
  62     description: Describes the CPU's local interrupt controller
  63
  64     properties:
  65       '#interrupt-cells':
  66         const: 1
  67
  68       compatible:
  69         const: riscv,cpu-intc
  70
  71       interrupt-controller: true
  72
  73     required:
  74       - '#interrupt-cells'
  75       - compatible
  76       - interrupt-controller
  77
  78 required:
  79   - riscv,isa
  80   - timebase-frequency
  81   - interrupt-controller
  82
  83 examples:
  84   - |
  85     // Example 1: SiFive Freedom U540G Development Kit
  86     cpus {
  87         #address-cells = <1>;
  88         #size-cells = <0>;
  89         timebase-frequency = <1000000>;
  90         cpu@0 {
  91                 clock-frequency = <0>;
  92                 compatible = "sifive,rocket0", "riscv";
  93                 device_type = "cpu";
  94                 i-cache-block-size = <64>;
  95                 i-cache-sets = <128>;
  96                 i-cache-size = <16384>;
  97                 reg = <0>;
  98                 riscv,isa = "rv64imac";
  99                 cpu_intc0: interrupt-controller {
 100                         #interrupt-cells = <1>;
 101                         compatible = "riscv,cpu-intc";
 102                         interrupt-controller;
 103                 };
 104         };
 105         cpu@1 {
 106                 clock-frequency = <0>;
 107                 compatible = "sifive,rocket0", "riscv";
 108                 d-cache-block-size = <64>;
 109                 d-cache-sets = <64>;
 110                 d-cache-size = <32768>;
 111                 d-tlb-sets = <1>;
 112                 d-tlb-size = <32>;
 113                 device_type = "cpu";
 114                 i-cache-block-size = <64>;
 115                 i-cache-sets = <64>;
 116                 i-cache-size = <32768>;
 117                 i-tlb-sets = <1>;
 118                 i-tlb-size = <32>;
 119                 mmu-type = "riscv,sv39";
 120                 reg = <1>;
 121                 riscv,isa = "rv64imafdc";
 122                 tlb-split;
 123                 cpu_intc1: interrupt-controller {
 124                         #interrupt-cells = <1>;
 125                         compatible = "riscv,cpu-intc";
 126                         interrupt-controller;
 127                 };
 128         };
 129     };
 130
 131   - |
 132     // Example 2: Spike ISA Simulator with 1 Hart
 133     cpus {
 134         #address-cells = <1>;
 135         #size-cells = <0>;
 136         cpu@0 {
 137                 device_type = "cpu";
 138                 reg = <0>;
 139                 compatible = "riscv";
 140                 riscv,isa = "rv64imafdc";
 141                 mmu-type = "riscv,sv48";
 142                 interrupt-controller {
 143                         #interrupt-cells = <1>;
 144                         interrupt-controller;
 145                         compatible = "riscv,cpu-intc";
 146                 };
 147         };
 148     };
 149 ...