1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp"
6 - reg Offset and length of the register set for the device
7 - interrupts There should be at least two interrupts. Some devices
8 have as many as four PTP related interrupts.
12 - fsl,cksel Timer reference clock source.
13 - fsl,tclk-period Timer reference clock period in nanoseconds.
14 - fsl,tmr-prsc Prescaler, divides the output clock.
15 - fsl,tmr-add Frequency compensation value.
16 - fsl,tmr-fiper1 Fixed interval period pulse generator.
17 - fsl,tmr-fiper2 Fixed interval period pulse generator.
18 - fsl,max-adj Maximum frequency adjustment in parts per billion.
20 These properties set the operational parameters for the PTP
21 clock. You must choose these carefully for the clock to work right.
22 Here is how to figure good values:
24 TimerOsc = selected reference clock MHz
25 tclk_period = desired clock period nanoseconds
26 NominalFreq = 1000 / tclk_period MHz
27 FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
28 tmr_add = ceil(2^32 / FreqDivRatio)
29 OutputClock = NominalFreq / tmr_prsc MHz
30 PulseWidth = 1 / OutputClock microseconds
31 FiperFreq1 = desired frequency in Hz
32 FiperDiv1 = 1000000 * OutputClock / FiperFreq1
33 tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
34 max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
36 The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
37 driver expects that tmr_fiper1 will be correctly set to produce a 1
38 Pulse Per Second (PPS) signal, since this will be offered to the PPS
39 subsystem to synchronize the Linux clock.
41 Reference clock source is determined by the value, which is holded
42 in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
43 value, which will be directly written in those bits, that is why,
44 according to reference manual, the next clock sources can be used:
46 <0> - external high precision timer reference clock (TSEC_TMR_CLK
47 input is used for this purpose);
48 <1> - eTSEC system clock;
49 <2> - eTSEC1 transmit clock;
50 <3> - RTC clock input.
52 When this attribute is not used, eTSEC system clock will serve as
53 IEEE 1588 timer reference clock.
58 compatible = "fsl,etsec-ptp";
60 interrupts = <12 0x8 13 0x8>;
61 interrupt-parent = < &ipic >;
63 fsl,tclk-period = <10>;
65 fsl,tmr-add = <0x999999A4>;
66 fsl,tmr-fiper1 = <0x3B9AC9F6>;
67 fsl,tmr-fiper2 = <0x00018696>;
68 fsl,max-adj = <659999998>;