1 * STM32 GPIO and Pin Mux/Config controller
3 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
4 controller. It controls the input/output settings on the available pins and
5 also provides ability to multiplex and configure the output of various on-chip
6 controllers onto these pads.
10 - compatible: value should be one of the following:
11 "st,stm32f429-pinctrl"
12 "st,stm32f746-pinctrl"
13 "st,stm32h743-pinctrl"
14 - #address-cells: The value of this property must be 1
15 - #size-cells : The value of this property must be 1
16 - ranges : defines mapping between pin controller node (parent) to
17 gpio-bank node (children).
18 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
21 GPIO controller/bank node:
23 - gpio-controller : Indicates this device is a GPIO controller
24 - #gpio-cells : Should be two.
25 The first cell is the pin number
26 The second one is the polarity:
29 - reg : The gpio address range, relative to the pinctrl range
30 - clocks : clock that drives this bank
31 - st,bank-name : Should be a name string for this bank as specified in
35 - reset: : Reference to the reset controller
36 - interrupt-parent: phandle of the interrupt parent to which the external
37 GPIO interrupts are forwarded to.
38 - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
39 which includes IRQ mux selection register, and the offset of the IRQ mux
41 - ngpios: Number of gpios in a bank (to use if bank gpio numbers is less
43 - gpio-ranges: Define a dedicated mapping between a pin-controller and
44 a gpio controller. Format is <&phandle a b c> with:
45 -(phandle): phandle of pin-controller.
46 -(a): gpio base offset in range.
47 -(b): pin base offset in range.
48 -(c): gpio count in range
49 This entry has to be used either if there are holes inside a bank:
50 GPIOB0/B1/B2/B14/B15 (see example 2)
51 or if banks are not contiguous:
53 NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller
54 have to use a "gpio-ranges" entry.
55 More details in Documentation/devicetree/bindings/gpio/gpio.txt.
58 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
64 compatible = "st,stm32f429-pinctrl";
65 ranges = <0 0x40020000 0x3000>;
68 gpioa: gpio@40020000 {
72 resets = <&reset_ahb1 0>;
73 st,bank-name = "GPIOA";
76 pin-functions nodes follow...
80 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
83 pinctrl: pin-controller {
86 compatible = "st,stm32f429-pinctrl";
87 ranges = <0 0x40020000 0x3000>;
90 gpioa: gpio@40020000 {
94 resets = <&reset_ahb1 0>;
95 st,bank-name = "GPIOA";
96 gpio-ranges = <&pinctrl 0 0 16>;
99 gpiob: gpio@40020400 {
103 resets = <&reset_ahb1 0>;
104 st,bank-name = "GPIOB";
106 gpio-ranges = <&pinctrl 0 16 3>,
112 pin-functions nodes follow...
116 Contents of function subnode node:
117 ----------------------------------
119 A pinctrl node should contain at least one subnode representing the
120 pinctrl group available on the machine. Each subnode will list the
121 pins it needs, and how they should be configured, with regard to muxer
122 configuration, pullups, drive, output high/low and output speed.
125 pinmux = <PIN_NUMBER_PINMUX>;
130 - pinmux: integer array, represents gpio pin number and mux setting.
131 Supported pin number and mux varies for different SoCs, and are defined in
132 dt-bindings/pinctrl/<soc>-pinfunc.h directly.
133 These defines are calculated as:
134 ((port * 16 + line) << 8) | function
136 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
137 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
138 - function: The function number, can be:
140 * 1 : Alternate Function 0
141 * 2 : Alternate Function 1
142 * 3 : Alternate Function 2
144 * 16 : Alternate Function 15
148 - GENERIC_PINCONFIG: is the generic pinconfig options to use.
149 Available options are:
157 - slew-rate = <x>, with x being:
167 usart1_pins_a: usart1@0 {
169 pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
175 pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
182 pinctrl-0 = <&usart1_pins_a>;
183 pinctrl-names = "default";