Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt

   1 == MediaTek MT7622 pinctrl controller ==
   2
   3 Required properties for the root node:
   4  - compatible: Should be one of the following
   5                "mediatek,mt7622-pinctrl" for MT7622 SoC
   6  - reg: offset and length of the pinctrl space
   7
   8  - gpio-controller: Marks the device node as a GPIO controller.
   9  - #gpio-cells: Should be two. The first cell is the pin number and the
  10    second is the GPIO flags.
  11
  12 Optional properties:
  13 - interrupt-controller  : Marks the device node as an interrupt controller
  14
  15 If the property interrupt-controller is defined, following property is required
  16 - reg-names: A string describing the "reg" entries. Must contain "eint".
  17 - interrupts : The interrupt output from the controller.
  18 - #interrupt-cells: Should be two.
  19
  20 Please refer to pinctrl-bindings.txt in this directory for details of the
  21 common pinctrl bindings used by client devices, including the meaning of the
  22 phrase "pin configuration node".
  23
  24 MT7622 pin configuration nodes act as a container for an arbitrary number of
  25 subnodes. Each of these subnodes represents some desired configuration for a
  26 pin, a group, or a list of pins or groups. This configuration can include the
  27 mux function to select on those pin(s)/group(s), and various pin configuration
  28 parameters, such as pull-up, slew rate, etc.
  29
  30 We support 2 types of configuration nodes. Those nodes can be either pinmux
  31 nodes or pinconf nodes. Each configuration node can consist of multiple nodes
  32 describing the pinmux and pinconf options.
  33
  34 The name of each subnode doesn't matter as long as it is unique; all subnodes
  35 should be enumerated and processed purely based on their content.
  36
  37 == pinmux nodes content ==
  38
  39 The following generic properties as defined in pinctrl-bindings.txt are valid
  40 to specify in a pinmux subnode:
  41
  42 Required properties are:
  43  - groups: An array of strings. Each string contains the name of a group.
  44   Valid values for these names are listed below.
  45  - function: A string containing the name of the function to mux to the
  46   group. Valid values for function names are listed below.
  47
  48 == pinconf nodes content ==
  49
  50 The following generic properties as defined in pinctrl-bindings.txt are valid
  51 to specify in a pinconf subnode:
  52
  53 Required properties are:
  54  - pins: An array of strings. Each string contains the name of a pin.
  55   Valid values for these names are listed below.
  56  - groups: An array of strings. Each string contains the name of a group.
  57   Valid values for these names are listed below.
  58
  59 Optional properies are:
  60  bias-disable, bias-pull, bias-pull-down, input-enable,
  61  input-schmitt-enable, input-schmitt-disable, output-enable
  62  output-low, output-high, drive-strength, slew-rate
  63
  64  Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for
  65  slower slew rate respectively.
  66  Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA.
  67
  68 The following specific properties as defined are valid to specify in a pinconf
  69 subnode:
  70
  71 Optional properties are:
  72  - mediatek,tdsel: An integer describing the steps for output level shifter duty
  73    cycle when asserted (high pulse width adjustment). Valid arguments are from 0
  74    to 15.
  75  - mediatek,rdsel: An integer describing the steps for input level shifter duty
  76    cycle when asserted (high pulse width adjustment). Valid arguments are from 0
  77    to 63.
  78
  79 == Valid values for pins, function and groups on MT7622 ==
  80
  81 Valid values for pins are:
  82 pins can be referenced via the pin names as the below table shown and the
  83 related physical number is also put ahead of those names which helps cross
  84 references to pins between groups to know whether pins assignment conflict
  85 happens among devices try to acquire those available pins.
  86
  87         Pin #:  Valid values for pins
  88         -----------------------------
  89         PIN 0: "GPIO_A"
  90         PIN 1: "I2S1_IN"
  91         PIN 2: "I2S1_OUT"
  92         PIN 3: "I2S_BCLK"
  93         PIN 4: "I2S_WS"
  94         PIN 5: "I2S_MCLK"
  95         PIN 6: "TXD0"
  96         PIN 7: "RXD0"
  97         PIN 8: "SPI_WP"
  98         PIN 9: "SPI_HOLD"
  99         PIN 10: "SPI_CLK"
 100         PIN 11: "SPI_MOSI"
 101         PIN 12: "SPI_MISO"
 102         PIN 13: "SPI_CS"
 103         PIN 14: "I2C_SDA"
 104         PIN 15: "I2C_SCL"
 105         PIN 16: "I2S2_IN"
 106         PIN 17: "I2S3_IN"
 107         PIN 18: "I2S4_IN"
 108         PIN 19: "I2S2_OUT"
 109         PIN 20: "I2S3_OUT"
 110         PIN 21: "I2S4_OUT"
 111         PIN 22: "GPIO_B"
 112         PIN 23: "MDC"
 113         PIN 24: "MDIO"
 114         PIN 25: "G2_TXD0"
 115         PIN 26: "G2_TXD1"
 116         PIN 27: "G2_TXD2"
 117         PIN 28: "G2_TXD3"
 118         PIN 29: "G2_TXEN"
 119         PIN 30: "G2_TXC"
 120         PIN 31: "G2_RXD0"
 121         PIN 32: "G2_RXD1"
 122         PIN 33: "G2_RXD2"
 123         PIN 34: "G2_RXD3"
 124         PIN 35: "G2_RXDV"
 125         PIN 36: "G2_RXC"
 126         PIN 37: "NCEB"
 127         PIN 38: "NWEB"
 128         PIN 39: "NREB"
 129         PIN 40: "NDL4"
 130         PIN 41: "NDL5"
 131         PIN 42: "NDL6"
 132         PIN 43: "NDL7"
 133         PIN 44: "NRB"
 134         PIN 45: "NCLE"
 135         PIN 46: "NALE"
 136         PIN 47: "NDL0"
 137         PIN 48: "NDL1"
 138         PIN 49: "NDL2"
 139         PIN 50: "NDL3"
 140         PIN 51: "MDI_TP_P0"
 141         PIN 52: "MDI_TN_P0"
 142         PIN 53: "MDI_RP_P0"
 143         PIN 54: "MDI_RN_P0"
 144         PIN 55: "MDI_TP_P1"
 145         PIN 56: "MDI_TN_P1"
 146         PIN 57: "MDI_RP_P1"
 147         PIN 58: "MDI_RN_P1"
 148         PIN 59: "MDI_RP_P2"
 149         PIN 60: "MDI_RN_P2"
 150         PIN 61: "MDI_TP_P2"
 151         PIN 62: "MDI_TN_P2"
 152         PIN 63: "MDI_TP_P3"
 153         PIN 64: "MDI_TN_P3"
 154         PIN 65: "MDI_RP_P3"
 155         PIN 66: "MDI_RN_P3"
 156         PIN 67: "MDI_RP_P4"
 157         PIN 68: "MDI_RN_P4"
 158         PIN 69: "MDI_TP_P4"
 159         PIN 70: "MDI_TN_P4"
 160         PIN 71: "PMIC_SCL"
 161         PIN 72: "PMIC_SDA"
 162         PIN 73: "SPIC1_CLK"
 163         PIN 74: "SPIC1_MOSI"
 164         PIN 75: "SPIC1_MISO"
 165         PIN 76: "SPIC1_CS"
 166         PIN 77: "GPIO_D"
 167         PIN 78: "WATCHDOG"
 168         PIN 79: "RTS3_N"
 169         PIN 80: "CTS3_N"
 170         PIN 81: "TXD3"
 171         PIN 82: "RXD3"
 172         PIN 83: "PERST0_N"
 173         PIN 84: "PERST1_N"
 174         PIN 85: "WLED_N"
 175         PIN 86: "EPHY_LED0_N"
 176         PIN 87: "AUXIN0"
 177         PIN 88: "AUXIN1"
 178         PIN 89: "AUXIN2"
 179         PIN 90: "AUXIN3"
 180         PIN 91: "TXD4"
 181         PIN 92: "RXD4"
 182         PIN 93: "RTS4_N"
 183         PIN 94: "CST4_N"
 184         PIN 95: "PWM1"
 185         PIN 96: "PWM2"
 186         PIN 97: "PWM3"
 187         PIN 98: "PWM4"
 188         PIN 99: "PWM5"
 189         PIN 100: "PWM6"
 190         PIN 101: "PWM7"
 191         PIN 102: "GPIO_E"
 192
 193 Valid values for function are:
 194         "emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie",
 195         "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog"
 196
 197 Valid values for groups are:
 198 additional data is put followingly with valid value allowing us to know which
 199 applicable function and which relevant pins (in pin#) are able applied for that
 200 group.
 201
 202         Valid value                     function        pins (in pin#)
 203         -------------------------------------------------------------------------
 204         "emmc"                          "emmc"          40, 41, 42, 43, 44, 45,
 205                                                         47, 48, 49, 50
 206         "emmc_rst"                      "emmc"          37
 207         "esw"                           "eth"           51, 52, 53, 54, 55, 56,
 208                                                         57, 58, 59, 60, 61, 62,
 209                                                         63, 64, 65, 66, 67, 68,
 210                                                         69, 70
 211         "esw_p0_p1"                     "eth"           51, 52, 53, 54, 55, 56,
 212                                                         57, 58
 213         "esw_p2_p3_p4"                  "eth"           59, 60, 61, 62, 63, 64,
 214                                                         65, 66, 67, 68, 69, 70
 215         "rgmii_via_esw"                 "eth"           59, 60, 61, 62, 63, 64,
 216                                                         65, 66, 67, 68, 69, 70
 217         "rgmii_via_gmac1"               "eth"           59, 60, 61, 62, 63, 64,
 218                                                         65, 66, 67, 68, 69, 70
 219         "rgmii_via_gmac2"               "eth"           25, 26, 27, 28, 29, 30,
 220                                                         31, 32, 33, 34, 35, 36
 221         "mdc_mdio"                      "eth"           23, 24
 222         "i2c0"                          "i2c"           14, 15
 223         "i2c1_0"                        "i2c"           55, 56
 224         "i2c1_1"                        "i2c"           73, 74
 225         "i2c1_2"                        "i2c"           87, 88
 226         "i2c2_0"                        "i2c"           57, 58
 227         "i2c2_1"                        "i2c"           75, 76
 228         "i2c2_2"                        "i2c"           89, 90
 229         "i2s_in_mclk_bclk_ws"           "i2s"           3, 4, 5
 230         "i2s1_in_data"                  "i2s"           1
 231         "i2s2_in_data"                  "i2s"           16
 232         "i2s3_in_data"                  "i2s"           17
 233         "i2s4_in_data"                  "i2s"           18
 234         "i2s_out_mclk_bclk_ws"          "i2s"           3, 4, 5
 235         "i2s1_out_data"                 "i2s"           2
 236         "i2s2_out_data"                 "i2s"           19
 237         "i2s3_out_data"                 "i2s"           20
 238         "i2s4_out_data"                 "i2s"           21
 239         "ir_0_tx"                       "ir"            16
 240         "ir_1_tx"                       "ir"            59
 241         "ir_2_tx"                       "ir"            99
 242         "ir_0_rx"                       "ir"            17
 243         "ir_1_rx"                       "ir"            60
 244         "ir_2_rx"                       "ir"            100
 245         "ephy_leds"                     "led"           86, 91, 92, 93, 94
 246         "ephy0_led"                     "led"           86
 247         "ephy1_led"                     "led"           91
 248         "ephy2_led"                     "led"           92
 249         "ephy3_led"                     "led"           93
 250         "ephy4_led"                     "led"           94
 251         "wled"                          "led"           85
 252         "par_nand"                      "flash"         37, 38, 39, 40, 41, 42,
 253                                                         43, 44, 45, 46, 47, 48,
 254                                                         49, 50
 255         "snfi"                          "flash"         8, 9, 10, 11, 12, 13
 256         "spi_nor"                       "flash"         8, 9, 10, 11, 12, 13
 257         "pcie0_0_waken"                 "pcie"          14
 258         "pcie0_1_waken"                 "pcie"          79
 259         "pcie1_0_waken"                 "pcie"          14
 260         "pcie0_0_clkreq"                "pcie"          15
 261         "pcie0_1_clkreq"                "pcie"          80
 262         "pcie1_0_clkreq"                "pcie"          15
 263         "pcie0_pad_perst"               "pcie"          83
 264         "pcie1_pad_perst"               "pcie"          84
 265         "pmic_bus"                      "pmic"          71, 72
 266         "pwm_ch1_0"                     "pwm"           51
 267         "pwm_ch1_1"                     "pwm"           73
 268         "pwm_ch1_2"                     "pwm"           95
 269         "pwm_ch2_0"                     "pwm"           52
 270         "pwm_ch2_1"                     "pwm"           74
 271         "pwm_ch2_2"                     "pwm"           96
 272         "pwm_ch3_0"                     "pwm"           53
 273         "pwm_ch3_1"                     "pwm"           75
 274         "pwm_ch3_2"                     "pwm"           97
 275         "pwm_ch4_0"                     "pwm"           54
 276         "pwm_ch4_1"                     "pwm"           67
 277         "pwm_ch4_2"                     "pwm"           76
 278         "pwm_ch4_3"                     "pwm"           98
 279         "pwm_ch5_0"                     "pwm"           68
 280         "pwm_ch5_1"                     "pwm"           77
 281         "pwm_ch5_2"                     "pwm"           99
 282         "pwm_ch6_0"                     "pwm"           69
 283         "pwm_ch6_1"                     "pwm"           78
 284         "pwm_ch6_2"                     "pwm"           81
 285         "pwm_ch6_3"                     "pwm"           100
 286         "pwm_ch7_0"                     "pwm"           70
 287         "pwm_ch7_1"                     "pwm"           82
 288         "pwm_ch7_2"                     "pwm"           101
 289         "sd_0"                          "sd"            16, 17, 18, 19, 20, 21
 290         "sd_1"                          "sd"            25, 26, 27, 28, 29, 30
 291         "spic0_0"                       "spi"           63, 64, 65, 66
 292         "spic0_1"                       "spi"           79, 80, 81, 82
 293         "spic1_0"                       "spi"           67, 68, 69, 70
 294         "spic1_1"                       "spi"           73, 74, 75, 76
 295         "spic2_0_wp_hold"               "spi"           8, 9
 296         "spic2_0"                       "spi"           10, 11, 12, 13
 297         "tdm_0_out_mclk_bclk_ws"        "tdm"           8, 9, 10
 298         "tdm_0_in_mclk_bclk_ws"         "tdm"           11, 12, 13
 299         "tdm_0_out_data"                "tdm"           20
 300         "tdm_0_in_data"                 "tdm"           21
 301         "tdm_1_out_mclk_bclk_ws"        "tdm"           57, 58, 59
 302         "tdm_1_in_mclk_bclk_ws"         "tdm"           60, 61, 62
 303         "tdm_1_out_data"                "tdm"           55
 304         "tdm_1_in_data"                 "tdm"           56
 305         "uart0_0_tx_rx"                 "uart"          6, 7
 306         "uart1_0_tx_rx"                 "uart"          55, 56
 307         "uart1_0_rts_cts"               "uart"          57, 58
 308         "uart1_1_tx_rx"                 "uart"          73, 74
 309         "uart1_1_rts_cts"               "uart"          75, 76
 310         "uart2_0_tx_rx"                 "uart"          3, 4
 311         "uart2_0_rts_cts"               "uart"          1, 2
 312         "uart2_1_tx_rx"                 "uart"          51, 52
 313         "uart2_1_rts_cts"               "uart"          53, 54
 314         "uart2_2_tx_rx"                 "uart"          59, 60
 315         "uart2_2_rts_cts"               "uart"          61, 62
 316         "uart2_3_tx_rx"                 "uart"          95, 96
 317         "uart3_0_tx_rx"                 "uart"          57, 58
 318         "uart3_1_tx_rx"                 "uart"          81, 82
 319         "uart3_1_rts_cts"               "uart"          79, 80
 320         "uart4_0_tx_rx"                 "uart"          61, 62
 321         "uart4_1_tx_rx"                 "uart"          91, 92
 322         "uart4_1_rts_cts"               "uart"          93, 94
 323         "uart4_2_tx_rx"                 "uart"          97, 98
 324         "uart4_2_rts_cts"               "uart"          95, 96
 325         "watchdog"                      "watchdog"      78
 326
 327 Example:
 328
 329         pio: pinctrl@10211000 {
 330                 compatible = "mediatek,mt7622-pinctrl";
 331                 reg = <0 0x10211000 0 0x1000>;
 332                 gpio-controller;
 333                 #gpio-cells = <2>;
 334
 335                 pinctrl_eth_default: eth-default {
 336                         mux-mdio {
 337                                 groups = "mdc_mdio";
 338                                 function = "eth";
 339                                 drive-strength = <12>;
 340                         };
 341
 342                         mux-gmac2 {
 343                                 groups = "gmac2";
 344                                 function = "eth";
 345                                 drive-strength = <12>;
 346                         };
 347
 348                         mux-esw {
 349                                 groups = "esw";
 350                                 function = "eth";
 351                                 drive-strength = <8>;
 352                         };
 353
 354                         conf-mdio {
 355                                 pins = "MDC";
 356                                 bias-pull-up;
 357                         };
 358                 };
 359         };