1 Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY
2 -------------------------------------------------
5 - compatible : should be "samsung,s5pv210-mipi-video-phy";
6 - reg : offset and length of the MIPI DPHY register set;
7 - #phy-cells : from the generic phy bindings, must be 1;
9 For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
10 the PHY specifier identifies the PHY and its meaning is as follows:
16 Samsung EXYNOS SoC series Display Port PHY
17 -------------------------------------------------
20 - compatible : should be "samsung,exynos5250-dp-video-phy";
21 - reg : offset and length of the Display Port PHY register set;
22 - #phy-cells : from the generic PHY bindings, must be 0;
24 Samsung S5P/EXYNOS SoC series USB PHY
25 -------------------------------------------------
28 - compatible : should be one of the listed compatibles:
29 - "samsung,exynos3250-usb2-phy"
30 - "samsung,exynos4210-usb2-phy"
31 - "samsung,exynos4x12-usb2-phy"
32 - "samsung,exynos5250-usb2-phy"
33 - reg : a list of registers used by phy driver
34 - first and obligatory is the location of phy modules registers
35 - samsung,sysreg-phandle - handle to syscon used to control the system registers
36 - samsung,pmureg-phandle - handle to syscon used to control PMU registers
37 - #phy-cells : from the generic phy bindings, must be 1;
38 - clocks and clock-names:
39 - the "phy" clock is required by the phy module, used as a gate
40 - the "ref" clock is used to get the rate of the clock provided to the
43 The first phandle argument in the PHY specifier identifies the PHY, its
44 meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
45 and Exynos 4212) it is as follows:
46 0 - USB device ("device"),
47 1 - USB host ("host"),
50 Exynos3250 has only USB device phy available as phy 0.
52 Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
57 For Exynos 4412 (compatible with Exynos 4212):
59 usbphy: phy@125b0000 {
60 compatible = "samsung,exynos4x12-usb2-phy";
61 reg = <0x125b0000 0x100>;
62 clocks = <&clock 305>, <&clock 2>;
63 clock-names = "phy", "ref";
66 samsung,sysreg-phandle = <&sys_reg>;
67 samsung,pmureg-phandle = <&pmu_reg>;
70 Then the PHY can be used in other nodes such as:
72 phy-consumer@12340000 {
77 Refer to DT bindings documentation of particular PHY consumer devices for more
78 information about required PHYs and the way of specification.
80 Samsung SATA PHY Controller
81 ---------------------------
83 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
84 Each SATA PHY controller should have its own node.
87 - compatible : compatible list, contains "samsung,exynos5250-sata-phy"
88 - reg : offset and length of the SATA PHY register set;
89 - #phy-cells : must be zero
90 - clocks : must be exactly one entry
91 - clock-names : must be "sata_phyctrl"
92 - samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
93 - samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
96 sata_phy: sata-phy@12170000 {
97 compatible = "samsung,exynos5250-sata-phy";
98 reg = <0x12170000 0x1ff>;
99 clocks = <&clock 287>;
100 clock-names = "sata_phyctrl";
102 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
103 samsung,syscon-phandle = <&pmu_syscon>;
106 Device-Tree bindings for sataphy i2c client driver
107 --------------------------------------------------
110 compatible: Should be "samsung,exynos-sataphy-i2c"
111 - reg: I2C address of the sataphy i2c device.
115 sata_phy_i2c:sata-phy@38 {
116 compatible = "samsung,exynos-sataphy-i2c";
120 Samsung Exynos5 SoC series USB DRD PHY controller
121 --------------------------------------------------
124 - compatible : Should be set to one of the following supported values:
125 - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
126 - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
127 - reg : Register offset and length of USB DRD PHY register set;
128 - clocks: Clock IDs array as required by the controller
129 - clock-names: names of clocks correseponding to IDs in the clock property;
131 - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
132 used for register access.
133 - ref: PHY's reference clock (usually crystal clock), used for
134 PHY operations, associated by phy name. It is used to
135 determine bit values for clock settings register.
136 For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
137 - samsung,pmu-syscon: phandle for PMU system controller interface, used to
138 control pmu registers for power isolation.
139 - #phy-cells : from the generic PHY bindings, must be 1;
141 For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
142 compatible PHYs, the second cell in the PHY specifier identifies the
143 PHY id, which is interpreted as follows:
148 usbdrd_phy: usbphy@12100000 {
149 compatible = "samsung,exynos5250-usbdrd-phy";
150 reg = <0x12100000 0x100>;
151 clocks = <&clock 286>, <&clock 1>;
152 clock-names = "phy", "ref";
153 samsung,pmu-syscon = <&pmu_system_controller>;
157 - aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
158 'usbdrd_phy' nodes should have numbered alias in the aliases node,
159 in the form of usbdrdphyN, N = 0, 1... (depending on number of
163 usbdrdphy0 = &usb3_phy0;
164 usbdrdphy1 = &usb3_phy1;