1 Qualcomm QMP PHY controller
2 ===========================
4 QMP phy controller supports physical layer functionality for a number of
5 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
8 - compatible: compatible list, contains:
9 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11 "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12 "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
13 "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
14 "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
17 - index 0: address and length of register set for PHY's common
19 - index 1: address and length of the DP_COM control block (for
20 "qcom,sdm845-qmp-usb3-phy" only).
23 - For "qcom,sdm845-qmp-usb3-phy":
24 - Should be: "reg-base", "dp_com"
26 - The reg-names property shouldn't be defined.
28 - #address-cells: must be 1
29 - #size-cells: must be 1
30 - ranges: must be present
32 - clocks: a list of phandles and clock-specifier pairs,
33 one for each entry in clock-names.
34 - clock-names: "cfg_ahb" for phy config clock,
35 "aux" for phy aux clock,
36 "ref" for 19.2 MHz ref clk,
37 "com_aux" for phy common block aux clock,
38 "ref_aux" for phy reference aux clock,
40 For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
41 For "qcom,msm8996-qmp-pcie-phy" must contain:
42 "aux", "cfg_ahb", "ref".
43 For "qcom,msm8996-qmp-usb3-phy" must contain:
44 "aux", "cfg_ahb", "ref".
45 For "qcom,sdm845-qmp-usb3-phy" must contain:
46 "aux", "cfg_ahb", "ref", "com_aux".
47 For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
48 "aux", "cfg_ahb", "ref", "com_aux".
49 For "qcom,sdm845-qmp-ufs-phy" must contain:
52 - resets: a list of phandles and reset controller specifier pairs,
53 one for each entry in reset-names.
54 - reset-names: "phy" for reset of phy block,
55 "common" for phy common block reset,
56 "cfg" for phy's ahb cfg block reset.
58 For "qcom,ipq8074-qmp-pcie-phy" must contain:
60 For "qcom,msm8996-qmp-pcie-phy" must contain:
61 "phy", "common", "cfg".
62 For "qcom,msm8996-qmp-usb3-phy" must contain
64 For "qcom,sdm845-qmp-usb3-phy" must contain:
66 For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
68 For "qcom,sdm845-qmp-ufs-phy": no resets are listed.
70 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
71 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
74 - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
78 - Each device node of QMP phy is required to have as many child nodes as
79 the number of lanes the PHY has.
81 Required properties for child nodes of PCIe PHYs (one child per lane):
82 - reg: list of offset and length pairs of register sets for PHY blocks -
83 tx, rx, pcs, and pcs_misc (optional).
84 - #phy-cells: must be 0
86 Required properties for a single "lanes" child node of non-PCIe PHYs:
87 - reg: list of offset and length pairs of register sets for PHY blocks
89 tx, rx, pcs, and (optionally) pcs_misc
91 tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc
92 - #phy-cells: must be 0
94 Required properties for child node of PCIe and USB3 qmp phys:
95 - clocks: a list of phandles and clock-specifier pairs,
96 one for each entry in clock-names.
97 - clock-names: Must contain following:
98 "pipe<lane-number>" for pipe clock specific to each lane.
99 - clock-output-names: Name of the PHY clock that will be the parent for
100 the above pipe clock.
101 For "qcom,ipq8074-qmp-pcie-phy":
102 - "pcie20_phy0_pipe_clk" Pipe Clock parent
104 "pcie20_phy1_pipe_clk"
105 - #clock-cells: must be 0
106 - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
107 gate-controlled by the gcc.
109 Required properties for child node of PHYs with lane reset, AKA:
110 "qcom,msm8996-qmp-pcie-phy"
111 - resets: a list of phandles and reset controller specifier pairs,
112 one for each entry in reset-names.
113 - reset-names: Must contain following:
114 "lane<lane-number>" for reset specific to each lane.
118 compatible = "qcom,msm8996-qmp-pcie-phy";
119 reg = <0x34000 0x488>;
120 #address-cells = <1>;
124 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
125 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
126 <&gcc GCC_PCIE_CLKREF_CLK>;
127 clock-names = "aux", "cfg_ahb", "ref";
129 vdda-phy-supply = <&pm8994_l28>;
130 vdda-pll-supply = <&pm8994_l12>;
132 resets = <&gcc GCC_PCIE_PHY_BCR>,
133 <&gcc GCC_PCIE_PHY_COM_BCR>,
134 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
135 reset-names = "phy", "common", "cfg";
137 pciephy_0: lane@35000 {
138 reg = <0x35000 0x130>,
144 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
145 clock-names = "pipe0";
146 clock-output-names = "pcie_0_pipe_clk_src";
147 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
148 reset-names = "lane0";
151 pciephy_1: lane@36000 {
157 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
158 reg = <0x88eb000 0x18c>;
159 #address-cells = <1>;
163 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
164 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
165 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
166 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
167 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
169 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
170 <&gcc GCC_USB3_PHY_SEC_BCR>;
171 reset-names = "phy", "common";
174 reg = <0x88eb200 0x128>,
180 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
181 clock-names = "pipe0";
182 clock-output-names = "usb3_uni_phy_pipe_clk_src";
187 compatible = "qcom,sdm845-qmp-ufs-phy";
188 reg = <0x1d87000 0x18c>;
189 #address-cells = <1>;
194 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
195 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
198 reg = <0x1d87400 0x108>,