Documentation/devicetree/bindings/nvmem/imx-ocotp.txt

   1 Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
   2
   3 This binding represents the on-chip eFuse OTP controller found on
   4 i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL,
   5 i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN and i.MX8MP SoCs.
   6
   7 Required properties:
   8 - compatible: should be one of
   9         "fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
  10         "fsl,imx6sl-ocotp" (i.MX6SL), or
  11         "fsl,imx6sx-ocotp" (i.MX6SX),
  12         "fsl,imx6ul-ocotp" (i.MX6UL),
  13         "fsl,imx6ull-ocotp" (i.MX6ULL/ULZ),
  14         "fsl,imx7d-ocotp" (i.MX7D/S),
  15         "fsl,imx6sll-ocotp" (i.MX6SLL),
  16         "fsl,imx7ulp-ocotp" (i.MX7ULP),
  17         "fsl,imx8mq-ocotp" (i.MX8MQ),
  18         "fsl,imx8mm-ocotp" (i.MX8MM),
  19         "fsl,imx8mn-ocotp" (i.MX8MN),
  20         "fsl,imx8mp-ocotp" (i.MX8MP),
  21         followed by "syscon".
  22 - #address-cells : Should be 1
  23 - #size-cells : Should be 1
  24 - reg: Should contain the register base and length.
  25 - clocks: Should contain a phandle pointing to the gated peripheral clock.
  26
  27 Optional properties:
  28 - read-only: disable write access
  29
  30 Optional Child nodes:
  31
  32 - Data cells of ocotp:
  33   Detailed bindings are described in bindings/nvmem/nvmem.txt
  34
  35 Example:
  36         ocotp: ocotp@21bc000 {
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 compatible = "fsl,imx6sx-ocotp", "syscon";
  40                 reg = <0x021bc000 0x4000>;
  41                 clocks = <&clks IMX6SX_CLK_OCOTP>;
  42
  43                 tempmon_calib: calib@38 {
  44                         reg = <0x38 4>;
  45                 };
  46
  47                 tempmon_temp_grade: temp-grade@20 {
  48                         reg = <0x20 4>;
  49                 };
  50         };