Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt

   1 * Qualcomm Atheros ath10k wireless devices
   2
   3 Required properties:
   4 - compatible: Should be one of the following:
   5         * "qcom,ath10k"
   6         * "qcom,ipq4019-wifi"
   7         * "qcom,wcn3990-wifi"
   8
   9 PCI based devices uses compatible string "qcom,ath10k" and takes calibration
  10 data along with board specific data via "qcom,ath10k-calibration-data".
  11 Rest of the properties are not applicable for PCI based devices.
  12
  13 AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"
  14 and also uses most of the properties defined in this doc (except
  15 "qcom,ath10k-calibration-data"). It uses "qcom,ath10k-pre-calibration-data"
  16 to carry pre calibration data.
  17
  18 In general, entry "qcom,ath10k-pre-calibration-data" and
  19 "qcom,ath10k-calibration-data" conflict with each other and only one
  20 can be provided per device.
  21
  22 SNOC based devices (i.e. wcn3990) uses compatible string "qcom,wcn3990-wifi".
  23
  24 Optional properties:
  25 - reg: Address and length of the register set for the device.
  26 - reg-names: Must include the list of following reg names,
  27              "membase"
  28 - resets: Must contain an entry for each entry in reset-names.
  29           See ../reset/reseti.txt for details.
  30 - reset-names: Must include the list of following reset names,
  31                "wifi_cpu_init"
  32                "wifi_radio_srif"
  33                "wifi_radio_warm"
  34                "wifi_radio_cold"
  35                "wifi_core_warm"
  36                "wifi_core_cold"
  37 - clocks: List of clock specifiers, must contain an entry for each required
  38           entry in clock-names.
  39 - clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref",
  40                "wifi_wcss_rtc".
  41 - interrupts: List of interrupt lines. Must contain an entry
  42               for each entry in the interrupt-names property.
  43 - interrupt-names: Must include the entries for MSI interrupt
  44                    names ("msi0" to "msi15") and legacy interrupt
  45                    name ("legacy"),
  46 - qcom,msi_addr: MSI interrupt address.
  47 - qcom,msi_base: Base value to add before writing MSI data into
  48                 MSI address register.
  49 - qcom,ath10k-calibration-variant: string to search for in the board-2.bin
  50                                    variant list with the same bus and device
  51                                    specific ids
  52 - qcom,ath10k-calibration-data : calibration data + board specific data
  53                                  as an array, the length can vary between
  54                                  hw versions.
  55 - qcom,ath10k-pre-calibration-data : pre calibration data as an array,
  56                                      the length can vary between hw versions.
  57 - <supply-name>-supply: handle to the regulator device tree node
  58                            optional "supply-name" is "vdd-0.8-cx-mx".
  59
  60 Example (to supply the calibration data alone):
  61
  62 In this example, the node is defined as child node of the PCI controller.
  63
  64 pci {
  65         pcie@0 {
  66                 reg = <0 0 0 0 0>;
  67                 #interrupt-cells = <1>;
  68                 #size-cells = <2>;
  69                 #address-cells = <3>;
  70                 device_type = "pci";
  71
  72                 ath10k@0,0 {
  73                         reg = <0 0 0 0 0>;
  74                         device_type = "pci";
  75                         qcom,ath10k-calibration-data = [ 01 02 03 ... ];
  76                 };
  77         };
  78 };
  79
  80 Example (to supply ipq4019 SoC wifi block details):
  81
  82 wifi0: wifi@a000000 {
  83         compatible = "qcom,ipq4019-wifi";
  84         reg = <0xa000000 0x200000>;
  85         resets = <&gcc WIFI0_CPU_INIT_RESET>,
  86                  <&gcc WIFI0_RADIO_SRIF_RESET>,
  87                  <&gcc WIFI0_RADIO_WARM_RESET>,
  88                  <&gcc WIFI0_RADIO_COLD_RESET>,
  89                  <&gcc WIFI0_CORE_WARM_RESET>,
  90                  <&gcc WIFI0_CORE_COLD_RESET>;
  91         reset-names = "wifi_cpu_init",
  92                       "wifi_radio_srif",
  93                       "wifi_radio_warm",
  94                       "wifi_radio_cold",
  95                       "wifi_core_warm",
  96                       "wifi_core_cold";
  97         clocks = <&gcc GCC_WCSS2G_CLK>,
  98                  <&gcc GCC_WCSS2G_REF_CLK>,
  99                  <&gcc GCC_WCSS2G_RTC_CLK>;
 100         clock-names = "wifi_wcss_cmd",
 101                       "wifi_wcss_ref",
 102                       "wifi_wcss_rtc";
 103         interrupts = <0 0x20 0x1>,
 104                      <0 0x21 0x1>,
 105                      <0 0x22 0x1>,
 106                      <0 0x23 0x1>,
 107                      <0 0x24 0x1>,
 108                      <0 0x25 0x1>,
 109                      <0 0x26 0x1>,
 110                      <0 0x27 0x1>,
 111                      <0 0x28 0x1>,
 112                      <0 0x29 0x1>,
 113                      <0 0x2a 0x1>,
 114                      <0 0x2b 0x1>,
 115                      <0 0x2c 0x1>,
 116                      <0 0x2d 0x1>,
 117                      <0 0x2e 0x1>,
 118                      <0 0x2f 0x1>,
 119                      <0 0xa8 0x0>;
 120         interrupt-names = "msi0",  "msi1",  "msi2",  "msi3",
 121                           "msi4",  "msi5",  "msi6",  "msi7",
 122                           "msi8",  "msi9",  "msi10", "msi11",
 123                           "msi12", "msi13", "msi14", "msi15",
 124                           "legacy";
 125         qcom,msi_addr = <0x0b006040>;
 126         qcom,msi_base = <0x40>;
 127         qcom,ath10k-pre-calibration-data = [ 01 02 03 ... ];
 128 };
 129
 130 Example (to supply wcn3990 SoC wifi block details):
 131
 132 wifi@18000000 {
 133                 compatible = "qcom,wcn3990-wifi";
 134                 reg = <0x18800000 0x800000>;
 135                 reg-names = "membase";
 136                 clocks = <&clock_gcc clk_aggre2_noc_clk>;
 137                 clock-names = "smmu_aggre2_noc_clk"
 138                 interrupts =
 139                            <0 130 0 /* CE0 */ >,
 140                            <0 131 0 /* CE1 */ >,
 141                            <0 132 0 /* CE2 */ >,
 142                            <0 133 0 /* CE3 */ >,
 143                            <0 134 0 /* CE4 */ >,
 144                            <0 135 0 /* CE5 */ >,
 145                            <0 136 0 /* CE6 */ >,
 146                            <0 137 0 /* CE7 */ >,
 147                            <0 138 0 /* CE8 */ >,
 148                            <0 139 0 /* CE9 */ >,
 149                            <0 140 0 /* CE10 */ >,
 150                            <0 141 0 /* CE11 */ >;
 151                 vdd-0.8-cx-mx-supply = <&pm8998_l5>;
 152 };