Documentation/devicetree/bindings/media/cedrus.txt

   1 Device-tree bindings for the VPU found in Allwinner SoCs, referred to as the
   2 Video Engine (VE) in Allwinner literature.
   3
   4 The VPU can only access the first 256 MiB of DRAM, that are DMA-mapped starting
   5 from the DRAM base. This requires specific memory allocation and handling.
   6
   7 Required properties:
   8 - compatible            : must be one of the following compatibles:
   9                         - "allwinner,sun4i-a10-video-engine"
  10                         - "allwinner,sun5i-a13-video-engine"
  11                         - "allwinner,sun7i-a20-video-engine"
  12                         - "allwinner,sun8i-a33-video-engine"
  13                         - "allwinner,sun8i-h3-video-engine"
  14 - reg                   : register base and length of VE;
  15 - clocks                : list of clock specifiers, corresponding to entries in
  16                           the clock-names property;
  17 - clock-names           : should contain "ahb", "mod" and "ram" entries;
  18 - resets                : phandle for reset;
  19 - interrupts            : VE interrupt number;
  20 - allwinner,sram        : SRAM region to use with the VE.
  21
  22 Optional properties:
  23 - memory-region         : CMA pool to use for buffers allocation instead of the
  24                           default CMA pool.
  25
  26 Example:
  27
  28 reserved-memory {
  29         #address-cells = <1>;
  30         #size-cells = <1>;
  31         ranges;
  32
  33         /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
  34         cma_pool: cma@4a000000 {
  35                 compatible = "shared-dma-pool";
  36                 size = <0x6000000>;
  37                 alloc-ranges = <0x4a000000 0x6000000>;
  38                 reusable;
  39                 linux,cma-default;
  40         };
  41 };
  42
  43 video-codec@1c0e000 {
  44         compatible = "allwinner,sun7i-a20-video-engine";
  45         reg = <0x01c0e000 0x1000>;
  46
  47         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
  48                  <&ccu CLK_DRAM_VE>;
  49         clock-names = "ahb", "mod", "ram";
  50
  51         resets = <&ccu RST_VE>;
  52         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
  53         allwinner,sram = <&ve_sram 1>;
  54 };