Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt

   1 ARM Mali Utgard GPU
   2 ===================
   3
   4 Required properties:
   5   - compatible
   6     * Must be one of the following:
   7       + "arm,mali-300"
   8       + "arm,mali-400"
   9       + "arm,mali-450"
  10     * And, optionally, one of the vendor specific compatible:
  11       + allwinner,sun4i-a10-mali
  12       + allwinner,sun7i-a20-mali
  13       + allwinner,sun8i-h3-mali
  14       + allwinner,sun50i-a64-mali
  15       + allwinner,sun50i-h5-mali
  16       + amlogic,meson8-mali
  17       + amlogic,meson8b-mali
  18       + amlogic,meson-gxbb-mali
  19       + amlogic,meson-gxl-mali
  20       + samsung,exynos4210-mali
  21       + rockchip,rk3036-mali
  22       + rockchip,rk3066-mali
  23       + rockchip,rk3188-mali
  24       + rockchip,rk3228-mali
  25       + rockchip,rk3328-mali
  26       + stericsson,db8500-mali
  27
  28   - reg: Physical base address and length of the GPU registers
  29
  30   - interrupts: an entry for each entry in interrupt-names.
  31     See ../interrupt-controller/interrupts.txt for details.
  32
  33   - interrupt-names:
  34     * ppX: Pixel Processor X interrupt (X from 0 to 7)
  35     * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
  36     * pp: Pixel Processor broadcast interrupt (mali-450 only)
  37     * gp: Geometry Processor interrupt
  38     * gpmmu: Geometry Processor MMU interrupt
  39
  40   - clocks: an entry for each entry in clock-names
  41   - clock-names:
  42     * bus: bus clock for the GPU
  43     * core: clock driving the GPU itself
  44
  45 Optional properties:
  46   - interrupt-names and interrupts:
  47     * pmu: Power Management Unit interrupt, if implemented in hardware
  48
  49   - memory-region:
  50     Memory region to allocate from, as defined in
  51     Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
  52
  53   - mali-supply:
  54     Phandle to regulator for the Mali device, as defined in
  55     Documentation/devicetree/bindings/regulator/regulator.txt for details.
  56
  57   - operating-points-v2:
  58     Operating Points for the GPU, as defined in
  59     Documentation/devicetree/bindings/opp/opp.txt
  60
  61   - power-domains:
  62     A power domain consumer specifier as defined in
  63     Documentation/devicetree/bindings/power/power_domain.txt
  64
  65 Vendor-specific bindings
  66 ------------------------
  67
  68 The Mali GPU is integrated very differently from one SoC to
  69 another. In order to accomodate those differences, you have the option
  70 to specify one more vendor-specific compatible, among:
  71
  72   - allwinner,sun4i-a10-mali
  73     Required properties:
  74       * resets: phandle to the reset line for the GPU
  75
  76   - allwinner,sun7i-a20-mali
  77     Required properties:
  78       * resets: phandle to the reset line for the GPU
  79
  80   - allwinner,sun50i-a64-mali
  81     Required properties:
  82       * resets: phandle to the reset line for the GPU
  83
  84   - allwinner,sun50i-h5-mali
  85     Required properties:
  86       * resets: phandle to the reset line for the GPU
  87
  88   - amlogic,meson8-mali and amlogic,meson8b-mali
  89     Required properties:
  90       * resets: phandle to the reset line for the GPU
  91
  92   - Rockchip variants:
  93     Required properties:
  94       * resets: phandle to the reset line for the GPU
  95
  96   - stericsson,db8500-mali
  97     Required properties:
  98       * interrupt-names and interrupts:
  99         + combined: combined interrupt of all of the above lines
 100
 101 Example:
 102
 103 mali: gpu@1c40000 {
 104         compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
 105         reg = <0x01c40000 0x10000>;
 106         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 107                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 108                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 109                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 110                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 111                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 112                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 113         interrupt-names = "gp",
 114                           "gpmmu",
 115                           "pp0",
 116                           "ppmmu0",
 117                           "pp1",
 118                           "ppmmu1",
 119                           "pmu";
 120         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 121         clock-names = "bus", "core";
 122         resets = <&ccu RST_BUS_GPU>;
 123 };
 124