1 Synopsys DesignWare AXI DMA Controller
4 - compatible: "snps,axi-dma-1.01a"
5 - reg: Address range of the DMAC registers. This should include
6 all of the per-channel registers.
7 - interrupt: Should contain the DMAC interrupt number.
8 - interrupt-parent: Should be the phandle for the interrupt controller
9 that services interrupts for this device.
10 - dma-channels: Number of channels supported by hardware.
11 - snps,dma-masters: Number of AXI masters supported by the hardware.
12 - snps,data-width: Maximum AXI data width supported by hardware.
13 (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
14 - snps,priority: Priority of channel. Array size is equal to the number of
15 dma-channels. Priority value must be programmed within [0:dma-channels-1]
16 range. (0 - minimum priority)
17 - snps,block-size: Maximum block size supported by the controller channel.
18 Array size is equal to the number of dma-channels.
21 - snps,axi-max-burst-len: Restrict master AXI burst length by value specified
22 in this property. If this property is missing the maximum AXI burst length
23 supported by DMAC is used. [1:256]
27 dmac: dma-controller@80000 {
28 compatible = "snps,axi-dma-1.01a";
29 reg = <0x80000 0x400>;
30 clocks = <&core_clk>, <&cfgr_clk>;
31 clock-names = "core-clk", "cfgr-clk";
32 interrupt-parent = <&intc>;
36 snps,dma-masters = <2>;
37 snps,data-width = <3>;
38 snps,block-size = <4096 4096 4096 4096>;
39 snps,priority = <0 1 2 3>;
40 snps,axi-max-burst-len = <16>;