Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt

   1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
   2 ================================
   3
   4 Required properties:
   5 - #address-cells: Should be <1>.
   6 - #size-cells: Should be <0>.
   7 - compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
   8               "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
   9 - reg: Represent the physical address range of the controller.
  10 - interrupts: Represent the controller's interrupt to the CPU(s).
  11 - clocks, clock-names: Phandles to the controller's pll reference
  12   clock(ref) and APB clock(pclk). For RK3399, a phy config clock
  13   (phy_cfg) and a grf clock(grf) are required. As described in [1].
  14 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
  15 - ports: contain a port node with endpoint definitions as defined in [2].
  16   For vopb,set the reg = <0> and set the reg = <1> for vopl.
  17 - video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
  18 - video port 1 for either a panel or subsequent encoder
  19
  20 Optional properties:
  21 - power-domains: a phandle to mipi dsi power domain node.
  22 - resets: list of phandle + reset specifier pairs, as described in [3].
  23 - reset-names: string reset name, must be "apb".
  24
  25 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  26 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
  27 [3] Documentation/devicetree/bindings/reset/reset.txt
  28
  29 Example:
  30         mipi_dsi: mipi@ff960000 {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
  34                 reg = <0xff960000 0x4000>;
  35                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  36                 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
  37                 clock-names = "ref", "pclk";
  38                 resets = <&cru SRST_MIPIDSI0>;
  39                 reset-names = "apb";
  40                 rockchip,grf = <&grf>;
  41
  42                 ports {
  43                         #address-cells = <1>;
  44                         #size-cells = <0>;
  45
  46                         mipi_in: port@0 {
  47                                 reg = <0>;
  48                                 #address-cells = <1>;
  49                                 #size-cells = <0>;
  50
  51                                 mipi_in_vopb: endpoint@0 {
  52                                         reg = <0>;
  53                                         remote-endpoint = <&vopb_out_mipi>;
  54                                 };
  55                                 mipi_in_vopl: endpoint@1 {
  56                                         reg = <1>;
  57                                         remote-endpoint = <&vopl_out_mipi>;
  58                                 };
  59                         };
  60
  61                         mipi_out: port@1 {
  62                                 reg = <1>;
  63                                 #address-cells = <1>;
  64                                 #size-cells = <0>;
  65
  66                                 mipi_out_panel: endpoint {
  67                                         remote-endpoint = <&panel_in_mipi>;
  68                                 };
  69                         };
  70                 };
  71
  72                 panel {
  73                         compatible ="boe,tv080wum-nl0";
  74                         reg = <0>;
  75
  76                         enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
  77                         pinctrl-names = "default";
  78                         pinctrl-0 = <&lcd_en>;
  79                         backlight = <&backlight>;
  80
  81                         port {
  82                                 panel_in_mipi: endpoint {
  83                                         remote-endpoint = <&mipi_out_panel>;
  84                                 };
  85                         };
  86                 };
  87         };