Documentation/devicetree/bindings/display/msm/gpu.txt

   1 Qualcomm adreno/snapdragon GPU
   2
   3 Required properties:
   4 - compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
   5               "amd,imageon-XYZ.W", "amd,imageon"
   6     for example: "qcom,adreno-306.0", "qcom,adreno"
   7   Note that you need to list the less specific "qcom,adreno" (since this
   8   is what the device is matched on), in addition to the more specific
   9   with the chip-id.
  10   If "amd,imageon" is used, there should be no top level msm device.
  11 - reg: Physical base address and length of the controller's registers.
  12 - interrupts: The interrupt signal from the gpu.
  13 - clocks: device clocks (if applicable)
  14   See ../clocks/clock-bindings.txt for details.
  15 - clock-names: the following clocks are required by a3xx, a4xx and a5xx
  16   cores:
  17   * "core"
  18   * "iface"
  19   * "mem_iface"
  20   For GMU attached devices the GPU clocks are not used and are not required. The
  21   following devices should not list clocks:
  22    - qcom,adreno-630.2
  23 - iommus: optional phandle to an adreno iommu instance
  24 - operating-points-v2: optional phandle to the OPP operating points
  25 - qcom,gmu: For GMU attached devices a phandle to the GMU device that will
  26   control the power for the GPU. Applicable targets:
  27     - qcom,adreno-630.2
  28
  29 Example 3xx/4xx/a5xx:
  30
  31 / {
  32         ...
  33
  34         gpu: qcom,kgsl-3d0@4300000 {
  35                 compatible = "qcom,adreno-320.2", "qcom,adreno";
  36                 reg = <0x04300000 0x20000>;
  37                 reg-names = "kgsl_3d0_reg_memory";
  38                 interrupts = <GIC_SPI 80 0>;
  39                 clock-names =
  40                     "core",
  41                     "iface",
  42                     "mem_iface";
  43                 clocks =
  44                     <&mmcc GFX3D_CLK>,
  45                     <&mmcc GFX3D_AHB_CLK>,
  46                     <&mmcc MMSS_IMEM_AHB_CLK>;
  47         };
  48 };
  49
  50 Example a6xx (with GMU):
  51
  52 / {
  53         ...
  54
  55         gpu@5000000 {
  56                 compatible = "qcom,adreno-630.2", "qcom,adreno";
  57                 #stream-id-cells = <16>;
  58
  59                 reg = <0x5000000 0x40000>, <0x509e000 0x10>;
  60                 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
  61
  62                 /*
  63                  * Look ma, no clocks! The GPU clocks and power are
  64                  * controlled entirely by the GMU
  65                  */
  66
  67                 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
  68
  69                 iommus = <&adreno_smmu 0>;
  70
  71                 operating-points-v2 = <&gpu_opp_table>;
  72
  73                 qcom,gmu = <&gmu>;
  74         };
  75 };