1 * Clock Block on Freescale CoreNet Platforms
3 Freescale CoreNet chips take primary clocking input from the external
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5 multiple phase locked loops (PLL) to create a variety of frequencies
6 which can then be passed to a variety of internal logic, including
7 cores and peripheral IP blocks.
8 Please refer to the Reference Manual for details.
10 1. Clock Block Binding
13 - compatible: Should contain a specific clock block compatible string
14 and a single chassis clock compatible string.
15 Clock block strings include, but not limited to, one of the:
16 * "fsl,p2041-clockgen"
17 * "fsl,p3041-clockgen"
18 * "fsl,p4080-clockgen"
19 * "fsl,p5020-clockgen"
20 * "fsl,p5040-clockgen"
21 * "fsl,t4240-clockgen"
22 * "fsl,b4420-clockgen"
23 * "fsl,b4860-clockgen"
24 Chassis clock strings include:
25 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
26 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
27 - reg: Describes the address of the device's resources within the
28 address space defined by its parent bus, and resource zero
29 represents the clock register set
30 - clock-frequency: Input system clock frequency
32 Recommended properties:
33 - ranges: Allows valid translation between child's address space and
34 parent's. Must be present if the device has sub-nodes.
35 - #address-cells: Specifies the number of cells used to represent
36 physical base addresses. Must be present if the device has
37 sub-nodes and set to 1 if present
38 - #size-cells: Specifies the number of cells used to represent
39 the size of an address. Must be present if the device has
40 sub-nodes and set to 1 if present
42 2. Clock Provider/Consumer Binding
44 Most of the bindings are from the common clock binding[1].
45 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
48 - compatible : Should include one of the following:
49 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
50 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
51 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
52 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
53 * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
54 It takes parent's clock-frequency as its clock.
55 * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
56 It takes parent's clock-frequency as its clock.
57 - #clock-cells: From common clock binding. The number of cells in a
58 clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
59 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
60 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
61 clock-specifier cell may take the following values:
62 * 0 - equal to the PLL frequency
63 * 1 - equal to the PLL frequency divided by 2
64 * 2 - equal to the PLL frequency divided by 4
66 Recommended properties:
67 - clocks: Should be the phandle of input parent clock
68 - clock-names: From common clock binding, indicates the clock name
69 - clock-output-names: From common clock binding, indicates the names of
71 - reg: Should be the offset and length of clock block base address.
72 The length should be 4.
74 Example for clock block and clock provider:
76 clockgen: global-utilities@e1000 {
77 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
78 ranges = <0x0 0xe1000 0x1000>;
79 clock-frequency = <133333333>;
80 reg = <0xe1000 0x1000>;
86 compatible = "fsl,qoriq-sysclk-1.0";
87 clock-output-names = "sysclk";
93 compatible = "fsl,qoriq-core-pll-1.0";
95 clock-output-names = "pll0", "pll0-div2";
101 compatible = "fsl,qoriq-core-pll-1.0";
103 clock-output-names = "pll1", "pll1-div2";
109 compatible = "fsl,qoriq-core-mux-1.0";
110 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
111 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
112 clock-output-names = "cmux0";
118 compatible = "fsl,qoriq-core-mux-1.0";
119 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
120 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
121 clock-output-names = "cmux1";
126 Example for clock consumer:
129 cpu0: PowerPC,e5500@0 {