1 Mediatek infracfg controller
2 ============================
4 The Mediatek infracfg controller provides various clocks and reset
9 - compatible: Should be one of:
10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6797-infracfg", "syscon"
13 - "mediatek,mt7622-infracfg", "syscon"
14 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
15 - "mediatek,mt8135-infracfg", "syscon"
16 - "mediatek,mt8173-infracfg", "syscon"
17 - #clock-cells: Must be 1
18 - #reset-cells: Must be 1
20 The infracfg controller uses the common clk binding from
21 Documentation/devicetree/bindings/clock/clock-bindings.txt
22 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
23 Also it uses the common reset controller binding from
24 Documentation/devicetree/bindings/reset/reset.txt.
25 The available reset outputs are defined in
26 dt-bindings/reset/mt*-resets.h
30 infracfg: power-controller@10001000 {
31 compatible = "mediatek,mt8173-infracfg", "syscon";
32 reg = <0 0x10001000 0 0x1000>;