1 Hisilicon Platforms Device Tree Bindings
2 ----------------------------------------------------
4 Required root node properties:
5 - compatible = "hisilicon,hi3660";
8 Required root node properties:
9 - compatible = "hisilicon,hi3798cv200";
11 Hi3798cv200 Poplar Board
12 Required root node properties:
13 - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
16 Required root node properties:
17 - compatible = "hisilicon,hi3620-hi4511";
20 Required root node properties:
21 - compatible = "hisilicon,hi6220";
24 Required root node properties:
25 - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
28 Required root node properties:
29 - compatible = "hisilicon,hip01-ca9x2";
32 Required root node properties:
33 - compatible = "hisilicon,hip04-d01";
36 Required root node properties:
37 - compatible = "hisilicon,hip05-d02";
40 Required root node properties:
41 - compatible = "hisilicon,hip06-d03";
44 Required root node properties:
45 - compatible = "hisilicon,hip07-d05";
47 Hisilicon system controller
50 - compatible : "hisilicon,sysctrl"
51 - reg : Register address and size
54 - smp-offset : offset in sysctrl for notifying slave cpu booting
58 If reg value is not zero, cpun exit wfi and go
59 - resume-offset : offset in sysctrl for notifying cpu0 when resume
60 - reboot-offset : offset in sysctrl for system reboot
65 sysctrl: system-controller@fc802000 {
66 compatible = "hisilicon,sysctrl";
67 reg = <0xfc802000 0x1000>;
69 resume-offset = <0x308>;
70 reboot-offset = <0x4>;
73 -----------------------------------------------------------------------
74 Hisilicon Hi6220 system controller
77 - compatible : "hisilicon,hi6220-sysctrl"
78 - reg : Register address and size
79 - #clock-cells: should be set to 1, many clock registers are defined
80 under this controller and this property must be present.
82 Hisilicon designs this controller as one of the system controllers,
83 its main functions are the same as Hisilicon system controller, but
84 the register offset of some core modules are different.
88 sys_ctrl: sys_ctrl@f7030000 {
89 compatible = "hisilicon,hi6220-sysctrl", "syscon";
90 reg = <0x0 0xf7030000 0x0 0x2000>;
95 Hisilicon Hi6220 Power Always ON domain controller
98 - compatible : "hisilicon,hi6220-aoctrl"
99 - reg : Register address and size
100 - #clock-cells: should be set to 1, many clock registers are defined
101 under this controller and this property must be present.
103 Hisilicon designs this system controller to control the power always
104 on domain for mobile platform.
108 ao_ctrl: ao_ctrl@f7800000 {
109 compatible = "hisilicon,hi6220-aoctrl", "syscon";
110 reg = <0x0 0xf7800000 0x0 0x2000>;
115 Hisilicon Hi6220 Media domain controller
118 - compatible : "hisilicon,hi6220-mediactrl"
119 - reg : Register address and size
120 - #clock-cells: should be set to 1, many clock registers are defined
121 under this controller and this property must be present.
123 Hisilicon designs this system controller to control the multimedia
124 domain(e.g. codec, G3D ...) for mobile platform.
128 media_ctrl: media_ctrl@f4410000 {
129 compatible = "hisilicon,hi6220-mediactrl", "syscon";
130 reg = <0x0 0xf4410000 0x0 0x1000>;
135 Hisilicon Hi6220 Power Management domain controller
138 - compatible : "hisilicon,hi6220-pmctrl"
139 - reg : Register address and size
140 - #clock-cells: should be set to 1, some clock registers are define
141 under this controller and this property must be present.
143 Hisilicon designs this system controller to control the power management
144 domain for mobile platform.
148 pm_ctrl: pm_ctrl@f7032000 {
149 compatible = "hisilicon,hi6220-pmctrl", "syscon";
150 reg = <0x0 0xf7032000 0x0 0x1000>;
155 Hisilicon Hi6220 SRAM controller
158 - compatible : "hisilicon,hi6220-sramctrl", "syscon"
159 - reg : Register address and size
161 Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
162 SRAM banks for power management, modem, security, etc. Further, use "syscon"
163 managing the common sram which can be shared by multiple modules.
167 sram: sram@fff80000 {
168 compatible = "hisilicon,hi6220-sramctrl", "syscon";
169 reg = <0x0 0xfff80000 0x0 0x12000>;
172 -----------------------------------------------------------------------
173 Hisilicon HiP01 system controller
176 - compatible : "hisilicon,hip01-sysctrl"
177 - reg : Register address and size
179 The HiP01 system controller is mostly compatible with hisilicon
180 system controller,but it has some specific control registers for
181 HIP01 SoC family, such as slave core boot, and also some same
182 registers located at different offset.
186 /* for hip01-ca9x2 */
187 sysctrl: system-controller@10000000 {
188 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
189 reg = <0x10000000 0x1000>;
190 reboot-offset = <0x4>;
193 -----------------------------------------------------------------------
194 Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
197 - compatible : "hisilicon,pcie-sas-subctrl", "syscon";
198 - reg : Register address and size
200 The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
201 HiP05 or HiP06 Soc to implement some basic configurations.
204 /* for HiP05 PCIe-SAS sub system */
205 pcie_sas: system_controller@b0000000 {
206 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
207 reg = <0xb0000000 0x10000>;
210 Hisilicon HiP05/HiP06 PERI sub system controller
213 - compatible : "hisilicon,peri-subctrl", "syscon";
214 - reg : Register address and size
216 The PERI sub system controller is shared by peripheral controllers in
217 HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
218 controllers include mdio, ddr, iic, uart, timer and so on.
221 /* for HiP05 sub peri system */
222 peri_c_subctrl: syscon@80000000 {
223 compatible = "hisilicon,peri-subctrl", "syscon";
224 reg = <0x0 0x80000000 0x0 0x10000>;
227 Hisilicon HiP05/HiP06 DSA sub system controller
230 - compatible : "hisilicon,dsa-subctrl", "syscon";
231 - reg : Register address and size
233 The DSA sub system controller is shared by peripheral controllers in
234 HiP05 or HiP06 Soc to implement some basic configurations.
237 /* for HiP05 dsa sub system */
238 pcie_sas: system_controller@a0000000 {
239 compatible = "hisilicon,dsa-subctrl", "syscon";
240 reg = <0xa0000000 0x10000>;
243 -----------------------------------------------------------------------
244 Hisilicon CPU controller
247 - compatible : "hisilicon,cpuctrl"
248 - reg : Register address and size
250 The clock registers and power registers of secondary cores are defined
251 in CPU controller, especially in HIX5HD2 SoC.
253 -----------------------------------------------------------------------
254 PCTRL: Peripheral misc control register
257 - compatible: "hisilicon,pctrl"
258 - reg: Address and size of pctrl.
263 pctrl: pctrl@fca09000 {
264 compatible = "hisilicon,pctrl";
265 reg = <0xfca09000 0x1000>;
268 -----------------------------------------------------------------------
272 - compatible: "hisilicon,hip04-fabric";
273 - reg: Address and size of Fabric
275 -----------------------------------------------------------------------
276 Bootwrapper boot method (software protocol on SMP):
279 - compatible: "hisilicon,hip04-bootwrapper";
280 - boot-method: Address and size of boot method.
281 [0]: bootwrapper physical address
282 [1]: bootwrapper size
283 [2]: relocation physical address