Documentation/devicetree/bindings/arm/cpus.txt

   1 =================
   2 ARM CPUs bindings
   3 =================
   4
   5 The device tree allows to describe the layout of CPUs in a system through
   6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   7 defining properties for every cpu.
   8
   9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
  10
  11 https://www.power.org/documentation/epapr-version-1-1/
  12
  13 with updates for 32-bit and 64-bit ARM systems provided in this document.
  14
  15 ================================
  16 Convention used in this document
  17 ================================
  18
  19 This document follows the conventions described in the ePAPR v1.1, with
  20 the addition:
  21
  22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  23   the reg property contained in bits 7 down to 0
  24
  25 =====================================
  26 cpus and cpu node bindings definition
  27 =====================================
  28
  29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
  30 nodes to be present and contain the properties described below.
  31
  32 - cpus node
  33
  34         Description: Container of cpu nodes
  35
  36         The node name must be "cpus".
  37
  38         A cpus node must define the following properties:
  39
  40         - #address-cells
  41                 Usage: required
  42                 Value type: <u32>
  43
  44                 Definition depends on ARM architecture version and
  45                 configuration:
  46
  47                         # On uniprocessor ARM architectures previous to v7
  48                           value must be 1, to enable a simple enumeration
  49                           scheme for processors that do not have a HW CPU
  50                           identification register.
  51                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
  52                           value must be 1, that corresponds to CPUID/MPIDR
  53                           registers sizes.
  54                         # On ARM v8 64-bit systems value should be set to 2,
  55                           that corresponds to the MPIDR_EL1 register size.
  56                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  57                           in the system, #address-cells can be set to 1, since
  58                           MPIDR_EL1[63:32] bits are not used for CPUs
  59                           identification.
  60         - #size-cells
  61                 Usage: required
  62                 Value type: <u32>
  63                 Definition: must be set to 0
  64
  65 - cpu node
  66
  67         Description: Describes a CPU in an ARM based system
  68
  69         PROPERTIES
  70
  71         - device_type
  72                 Usage: required
  73                 Value type: <string>
  74                 Definition: must be "cpu"
  75         - reg
  76                 Usage and definition depend on ARM architecture version and
  77                 configuration:
  78
  79                         # On uniprocessor ARM architectures previous to v7
  80                           this property is required and must be set to 0.
  81
  82                         # On ARM 11 MPcore based systems this property is
  83                           required and matches the CPUID[11:0] register bits.
  84
  85                           Bits [11:0] in the reg cell must be set to
  86                           bits [11:0] in CPU ID register.
  87
  88                           All other bits in the reg cell must be set to 0.
  89
  90                         # On 32-bit ARM v7 or later systems this property is
  91                           required and matches the CPU MPIDR[23:0] register
  92                           bits.
  93
  94                           Bits [23:0] in the reg cell must be set to
  95                           bits [23:0] in MPIDR.
  96
  97                           All other bits in the reg cell must be set to 0.
  98
  99                         # On ARM v8 64-bit systems this property is required
 100                           and matches the MPIDR_EL1 register affinity bits.
 101
 102                           * If cpus node's #address-cells property is set to 2
 103
 104                             The first reg cell bits [7:0] must be set to
 105                             bits [39:32] of MPIDR_EL1.
 106
 107                             The second reg cell bits [23:0] must be set to
 108                             bits [23:0] of MPIDR_EL1.
 109
 110                           * If cpus node's #address-cells property is set to 1
 111
 112                             The reg cell bits [23:0] must be set to bits [23:0]
 113                             of MPIDR_EL1.
 114
 115                           All other bits in the reg cells must be set to 0.
 116
 117         - compatible:
 118                 Usage: required
 119                 Value type: <string>
 120                 Definition: should be one of:
 121                             "arm,arm710t"
 122                             "arm,arm720t"
 123                             "arm,arm740t"
 124                             "arm,arm7ej-s"
 125                             "arm,arm7tdmi"
 126                             "arm,arm7tdmi-s"
 127                             "arm,arm9es"
 128                             "arm,arm9ej-s"
 129                             "arm,arm920t"
 130                             "arm,arm922t"
 131                             "arm,arm925"
 132                             "arm,arm926e-s"
 133                             "arm,arm926ej-s"
 134                             "arm,arm940t"
 135                             "arm,arm946e-s"
 136                             "arm,arm966e-s"
 137                             "arm,arm968e-s"
 138                             "arm,arm9tdmi"
 139                             "arm,arm1020e"
 140                             "arm,arm1020t"
 141                             "arm,arm1022e"
 142                             "arm,arm1026ej-s"
 143                             "arm,arm1136j-s"
 144                             "arm,arm1136jf-s"
 145                             "arm,arm1156t2-s"
 146                             "arm,arm1156t2f-s"
 147                             "arm,arm1176jzf"
 148                             "arm,arm1176jz-s"
 149                             "arm,arm1176jzf-s"
 150                             "arm,arm11mpcore"
 151                             "arm,cortex-a5"
 152                             "arm,cortex-a7"
 153                             "arm,cortex-a8"
 154                             "arm,cortex-a9"
 155                             "arm,cortex-a12"
 156                             "arm,cortex-a15"
 157                             "arm,cortex-a17"
 158                             "arm,cortex-a53"
 159                             "arm,cortex-a57"
 160                             "arm,cortex-a72"
 161                             "arm,cortex-m0"
 162                             "arm,cortex-m0+"
 163                             "arm,cortex-m1"
 164                             "arm,cortex-m3"
 165                             "arm,cortex-m4"
 166                             "arm,cortex-r4"
 167                             "arm,cortex-r5"
 168                             "arm,cortex-r7"
 169                             "brcm,brahma-b15"
 170                             "brcm,vulcan"
 171                             "cavium,thunder"
 172                             "faraday,fa526"
 173                             "intel,sa110"
 174                             "intel,sa1100"
 175                             "marvell,feroceon"
 176                             "marvell,mohawk"
 177                             "marvell,pj4a"
 178                             "marvell,pj4b"
 179                             "marvell,sheeva-v5"
 180                             "nvidia,tegra132-denver"
 181                             "nvidia,tegra186-denver"
 182                             "qcom,krait"
 183                             "qcom,kryo"
 184                             "qcom,scorpion"
 185         - enable-method
 186                 Value type: <stringlist>
 187                 Usage and definition depend on ARM architecture version.
 188                         # On ARM v8 64-bit this property is required and must
 189                           be one of:
 190                              "psci"
 191                              "spin-table"
 192                         # On ARM 32-bit systems this property is optional and
 193                           can be one of:
 194                             "allwinner,sun6i-a31"
 195                             "allwinner,sun8i-a23"
 196                             "arm,realview-smp"
 197                             "brcm,bcm11351-cpu-method"
 198                             "brcm,bcm23550"
 199                             "brcm,bcm-nsp-smp"
 200                             "brcm,brahma-b15"
 201                             "marvell,armada-375-smp"
 202                             "marvell,armada-380-smp"
 203                             "marvell,armada-390-smp"
 204                             "marvell,armada-xp-smp"
 205                             "mediatek,mt6589-smp"
 206                             "mediatek,mt81xx-tz-smp"
 207                             "qcom,gcc-msm8660"
 208                             "qcom,kpss-acc-v1"
 209                             "qcom,kpss-acc-v2"
 210                             "renesas,apmu"
 211                             "rockchip,rk3036-smp"
 212                             "rockchip,rk3066-smp"
 213                             "ste,dbx500-smp"
 214
 215         - cpu-release-addr
 216                 Usage: required for systems that have an "enable-method"
 217                        property value of "spin-table".
 218                 Value type: <prop-encoded-array>
 219                 Definition:
 220                         # On ARM v8 64-bit systems must be a two cell
 221                           property identifying a 64-bit zero-initialised
 222                           memory location.
 223
 224         - qcom,saw
 225                 Usage: required for systems that have an "enable-method"
 226                        property value of "qcom,kpss-acc-v1" or
 227                        "qcom,kpss-acc-v2"
 228                 Value type: <phandle>
 229                 Definition: Specifies the SAW[1] node associated with this CPU.
 230
 231         - qcom,acc
 232                 Usage: required for systems that have an "enable-method"
 233                        property value of "qcom,kpss-acc-v1" or
 234                        "qcom,kpss-acc-v2"
 235                 Value type: <phandle>
 236                 Definition: Specifies the ACC[2] node associated with this CPU.
 237
 238         - cpu-idle-states
 239                 Usage: Optional
 240                 Value type: <prop-encoded-array>
 241                 Definition:
 242                         # List of phandles to idle state nodes supported
 243                           by this cpu [3].
 244
 245         - capacity-dmips-mhz
 246                 Usage: Optional
 247                 Value type: <u32>
 248                 Definition:
 249                         # u32 value representing CPU capacity [3] in
 250                           DMIPS/MHz, relative to highest capacity-dmips-mhz
 251                           in the system.
 252
 253         - rockchip,pmu
 254                 Usage: optional for systems that have an "enable-method"
 255                        property value of "rockchip,rk3066-smp"
 256                        While optional, it is the preferred way to get access to
 257                        the cpu-core power-domains.
 258                 Value type: <phandle>
 259                 Definition: Specifies the syscon node controlling the cpu core
 260                             power domains.
 261
 262         - dynamic-power-coefficient
 263                 Usage: optional
 264                 Value type: <prop-encoded-array>
 265                 Definition: A u32 value that represents the running time dynamic
 266                             power coefficient in units of mW/MHz/uV^2. The
 267                             coefficient can either be calculated from power
 268                             measurements or derived by analysis.
 269
 270                             The dynamic power consumption of the CPU  is
 271                             proportional to the square of the Voltage (V) and
 272                             the clock frequency (f). The coefficient is used to
 273                             calculate the dynamic power as below -
 274
 275                             Pdyn = dynamic-power-coefficient * V^2 * f
 276
 277                             where voltage is in uV, frequency is in MHz.
 278
 279 Example 1 (dual-cluster big.LITTLE system 32-bit):
 280
 281         cpus {
 282                 #size-cells = <0>;
 283                 #address-cells = <1>;
 284
 285                 cpu@0 {
 286                         device_type = "cpu";
 287                         compatible = "arm,cortex-a15";
 288                         reg = <0x0>;
 289                 };
 290
 291                 cpu@1 {
 292                         device_type = "cpu";
 293                         compatible = "arm,cortex-a15";
 294                         reg = <0x1>;
 295                 };
 296
 297                 cpu@100 {
 298                         device_type = "cpu";
 299                         compatible = "arm,cortex-a7";
 300                         reg = <0x100>;
 301                 };
 302
 303                 cpu@101 {
 304                         device_type = "cpu";
 305                         compatible = "arm,cortex-a7";
 306                         reg = <0x101>;
 307                 };
 308         };
 309
 310 Example 2 (Cortex-A8 uniprocessor 32-bit system):
 311
 312         cpus {
 313                 #size-cells = <0>;
 314                 #address-cells = <1>;
 315
 316                 cpu@0 {
 317                         device_type = "cpu";
 318                         compatible = "arm,cortex-a8";
 319                         reg = <0x0>;
 320                 };
 321         };
 322
 323 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 324
 325         cpus {
 326                 #size-cells = <0>;
 327                 #address-cells = <1>;
 328
 329                 cpu@0 {
 330                         device_type = "cpu";
 331                         compatible = "arm,arm926ej-s";
 332                         reg = <0x0>;
 333                 };
 334         };
 335
 336 Example 4 (ARM Cortex-A57 64-bit system):
 337
 338 cpus {
 339         #size-cells = <0>;
 340         #address-cells = <2>;
 341
 342         cpu@0 {
 343                 device_type = "cpu";
 344                 compatible = "arm,cortex-a57";
 345                 reg = <0x0 0x0>;
 346                 enable-method = "spin-table";
 347                 cpu-release-addr = <0 0x20000000>;
 348         };
 349
 350         cpu@1 {
 351                 device_type = "cpu";
 352                 compatible = "arm,cortex-a57";
 353                 reg = <0x0 0x1>;
 354                 enable-method = "spin-table";
 355                 cpu-release-addr = <0 0x20000000>;
 356         };
 357
 358         cpu@100 {
 359                 device_type = "cpu";
 360                 compatible = "arm,cortex-a57";
 361                 reg = <0x0 0x100>;
 362                 enable-method = "spin-table";
 363                 cpu-release-addr = <0 0x20000000>;
 364         };
 365
 366         cpu@101 {
 367                 device_type = "cpu";
 368                 compatible = "arm,cortex-a57";
 369                 reg = <0x0 0x101>;
 370                 enable-method = "spin-table";
 371                 cpu-release-addr = <0 0x20000000>;
 372         };
 373
 374         cpu@10000 {
 375                 device_type = "cpu";
 376                 compatible = "arm,cortex-a57";
 377                 reg = <0x0 0x10000>;
 378                 enable-method = "spin-table";
 379                 cpu-release-addr = <0 0x20000000>;
 380         };
 381
 382         cpu@10001 {
 383                 device_type = "cpu";
 384                 compatible = "arm,cortex-a57";
 385                 reg = <0x0 0x10001>;
 386                 enable-method = "spin-table";
 387                 cpu-release-addr = <0 0x20000000>;
 388         };
 389
 390         cpu@10100 {
 391                 device_type = "cpu";
 392                 compatible = "arm,cortex-a57";
 393                 reg = <0x0 0x10100>;
 394                 enable-method = "spin-table";
 395                 cpu-release-addr = <0 0x20000000>;
 396         };
 397
 398         cpu@10101 {
 399                 device_type = "cpu";
 400                 compatible = "arm,cortex-a57";
 401                 reg = <0x0 0x10101>;
 402                 enable-method = "spin-table";
 403                 cpu-release-addr = <0 0x20000000>;
 404         };
 405
 406         cpu@100000000 {
 407                 device_type = "cpu";
 408                 compatible = "arm,cortex-a57";
 409                 reg = <0x1 0x0>;
 410                 enable-method = "spin-table";
 411                 cpu-release-addr = <0 0x20000000>;
 412         };
 413
 414         cpu@100000001 {
 415                 device_type = "cpu";
 416                 compatible = "arm,cortex-a57";
 417                 reg = <0x1 0x1>;
 418                 enable-method = "spin-table";
 419                 cpu-release-addr = <0 0x20000000>;
 420         };
 421
 422         cpu@100000100 {
 423                 device_type = "cpu";
 424                 compatible = "arm,cortex-a57";
 425                 reg = <0x1 0x100>;
 426                 enable-method = "spin-table";
 427                 cpu-release-addr = <0 0x20000000>;
 428         };
 429
 430         cpu@100000101 {
 431                 device_type = "cpu";
 432                 compatible = "arm,cortex-a57";
 433                 reg = <0x1 0x101>;
 434                 enable-method = "spin-table";
 435                 cpu-release-addr = <0 0x20000000>;
 436         };
 437
 438         cpu@100010000 {
 439                 device_type = "cpu";
 440                 compatible = "arm,cortex-a57";
 441                 reg = <0x1 0x10000>;
 442                 enable-method = "spin-table";
 443                 cpu-release-addr = <0 0x20000000>;
 444         };
 445
 446         cpu@100010001 {
 447                 device_type = "cpu";
 448                 compatible = "arm,cortex-a57";
 449                 reg = <0x1 0x10001>;
 450                 enable-method = "spin-table";
 451                 cpu-release-addr = <0 0x20000000>;
 452         };
 453
 454         cpu@100010100 {
 455                 device_type = "cpu";
 456                 compatible = "arm,cortex-a57";
 457                 reg = <0x1 0x10100>;
 458                 enable-method = "spin-table";
 459                 cpu-release-addr = <0 0x20000000>;
 460         };
 461
 462         cpu@100010101 {
 463                 device_type = "cpu";
 464                 compatible = "arm,cortex-a57";
 465                 reg = <0x1 0x10101>;
 466                 enable-method = "spin-table";
 467                 cpu-release-addr = <0 0x20000000>;
 468         };
 469 };
 470
 471 --
 472 [1] arm/msm/qcom,saw2.txt
 473 [2] arm/msm/qcom,kpss-acc.txt
 474 [3] ARM Linux kernel documentation - idle states bindings
 475     Documentation/devicetree/bindings/arm/idle-states.txt
 476 [3] ARM Linux kernel documentation - cpu capacity bindings
 477     Documentation/devicetree/bindings/arm/cpu-capacity.txt