Documentation/devicetree/bindings/arm/cpus.txt

   1 =================
   2 ARM CPUs bindings
   3 =================
   4
   5 The device tree allows to describe the layout of CPUs in a system through
   6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   7 defining properties for every cpu.
   8
   9 Bindings for CPU nodes follow the Devicetree Specification, available from:
  10
  11 https://www.devicetree.org/specifications/
  12
  13 with updates for 32-bit and 64-bit ARM systems provided in this document.
  14
  15 ================================
  16 Convention used in this document
  17 ================================
  18
  19 This document follows the conventions described in the Devicetree
  20 Specification, with the addition:
  21
  22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  23   the reg property contained in bits 7 down to 0
  24
  25 =====================================
  26 cpus and cpu node bindings definition
  27 =====================================
  28
  29 The ARM architecture, in accordance with the Devicetree Specification,
  30 requires the cpus and cpu nodes to be present and contain the properties
  31 described below.
  32
  33 - cpus node
  34
  35         Description: Container of cpu nodes
  36
  37         The node name must be "cpus".
  38
  39         A cpus node must define the following properties:
  40
  41         - #address-cells
  42                 Usage: required
  43                 Value type: <u32>
  44
  45                 Definition depends on ARM architecture version and
  46                 configuration:
  47
  48                         # On uniprocessor ARM architectures previous to v7
  49                           value must be 1, to enable a simple enumeration
  50                           scheme for processors that do not have a HW CPU
  51                           identification register.
  52                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
  53                           value must be 1, that corresponds to CPUID/MPIDR
  54                           registers sizes.
  55                         # On ARM v8 64-bit systems value should be set to 2,
  56                           that corresponds to the MPIDR_EL1 register size.
  57                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  58                           in the system, #address-cells can be set to 1, since
  59                           MPIDR_EL1[63:32] bits are not used for CPUs
  60                           identification.
  61         - #size-cells
  62                 Usage: required
  63                 Value type: <u32>
  64                 Definition: must be set to 0
  65
  66 - cpu node
  67
  68         Description: Describes a CPU in an ARM based system
  69
  70         PROPERTIES
  71
  72         - device_type
  73                 Usage: required
  74                 Value type: <string>
  75                 Definition: must be "cpu"
  76         - reg
  77                 Usage and definition depend on ARM architecture version and
  78                 configuration:
  79
  80                         # On uniprocessor ARM architectures previous to v7
  81                           this property is required and must be set to 0.
  82
  83                         # On ARM 11 MPcore based systems this property is
  84                           required and matches the CPUID[11:0] register bits.
  85
  86                           Bits [11:0] in the reg cell must be set to
  87                           bits [11:0] in CPU ID register.
  88
  89                           All other bits in the reg cell must be set to 0.
  90
  91                         # On 32-bit ARM v7 or later systems this property is
  92                           required and matches the CPU MPIDR[23:0] register
  93                           bits.
  94
  95                           Bits [23:0] in the reg cell must be set to
  96                           bits [23:0] in MPIDR.
  97
  98                           All other bits in the reg cell must be set to 0.
  99
 100                         # On ARM v8 64-bit systems this property is required
 101                           and matches the MPIDR_EL1 register affinity bits.
 102
 103                           * If cpus node's #address-cells property is set to 2
 104
 105                             The first reg cell bits [7:0] must be set to
 106                             bits [39:32] of MPIDR_EL1.
 107
 108                             The second reg cell bits [23:0] must be set to
 109                             bits [23:0] of MPIDR_EL1.
 110
 111                           * If cpus node's #address-cells property is set to 1
 112
 113                             The reg cell bits [23:0] must be set to bits [23:0]
 114                             of MPIDR_EL1.
 115
 116                           All other bits in the reg cells must be set to 0.
 117
 118         - compatible:
 119                 Usage: required
 120                 Value type: <string>
 121                 Definition: should be one of:
 122                             "arm,arm710t"
 123                             "arm,arm720t"
 124                             "arm,arm740t"
 125                             "arm,arm7ej-s"
 126                             "arm,arm7tdmi"
 127                             "arm,arm7tdmi-s"
 128                             "arm,arm9es"
 129                             "arm,arm9ej-s"
 130                             "arm,arm920t"
 131                             "arm,arm922t"
 132                             "arm,arm925"
 133                             "arm,arm926e-s"
 134                             "arm,arm926ej-s"
 135                             "arm,arm940t"
 136                             "arm,arm946e-s"
 137                             "arm,arm966e-s"
 138                             "arm,arm968e-s"
 139                             "arm,arm9tdmi"
 140                             "arm,arm1020e"
 141                             "arm,arm1020t"
 142                             "arm,arm1022e"
 143                             "arm,arm1026ej-s"
 144                             "arm,arm1136j-s"
 145                             "arm,arm1136jf-s"
 146                             "arm,arm1156t2-s"
 147                             "arm,arm1156t2f-s"
 148                             "arm,arm1176jzf"
 149                             "arm,arm1176jz-s"
 150                             "arm,arm1176jzf-s"
 151                             "arm,arm11mpcore"
 152                             "arm,cortex-a5"
 153                             "arm,cortex-a7"
 154                             "arm,cortex-a8"
 155                             "arm,cortex-a9"
 156                             "arm,cortex-a12"
 157                             "arm,cortex-a15"
 158                             "arm,cortex-a17"
 159                             "arm,cortex-a53"
 160                             "arm,cortex-a57"
 161                             "arm,cortex-a72"
 162                             "arm,cortex-a73"
 163                             "arm,cortex-m0"
 164                             "arm,cortex-m0+"
 165                             "arm,cortex-m1"
 166                             "arm,cortex-m3"
 167                             "arm,cortex-m4"
 168                             "arm,cortex-r4"
 169                             "arm,cortex-r5"
 170                             "arm,cortex-r7"
 171                             "brcm,brahma-b15"
 172                             "brcm,brahma-b53"
 173                             "brcm,vulcan"
 174                             "cavium,thunder"
 175                             "cavium,thunder2"
 176                             "faraday,fa526"
 177                             "intel,sa110"
 178                             "intel,sa1100"
 179                             "marvell,feroceon"
 180                             "marvell,mohawk"
 181                             "marvell,pj4a"
 182                             "marvell,pj4b"
 183                             "marvell,sheeva-v5"
 184                             "nvidia,tegra132-denver"
 185                             "nvidia,tegra186-denver"
 186                             "qcom,krait"
 187                             "qcom,kryo"
 188                             "qcom,kryo385"
 189                             "qcom,scorpion"
 190         - enable-method
 191                 Value type: <stringlist>
 192                 Usage and definition depend on ARM architecture version.
 193                         # On ARM v8 64-bit this property is required and must
 194                           be one of:
 195                              "psci"
 196                              "spin-table"
 197                         # On ARM 32-bit systems this property is optional and
 198                           can be one of:
 199                             "actions,s500-smp"
 200                             "allwinner,sun6i-a31"
 201                             "allwinner,sun8i-a23"
 202                             "allwinner,sun9i-a80-smp"
 203                             "amlogic,meson8-smp"
 204                             "amlogic,meson8b-smp"
 205                             "arm,realview-smp"
 206                             "brcm,bcm11351-cpu-method"
 207                             "brcm,bcm23550"
 208                             "brcm,bcm2836-smp"
 209                             "brcm,bcm-nsp-smp"
 210                             "brcm,brahma-b15"
 211                             "marvell,armada-375-smp"
 212                             "marvell,armada-380-smp"
 213                             "marvell,armada-390-smp"
 214                             "marvell,armada-xp-smp"
 215                             "marvell,98dx3236-smp"
 216                             "mediatek,mt6589-smp"
 217                             "mediatek,mt81xx-tz-smp"
 218                             "qcom,gcc-msm8660"
 219                             "qcom,kpss-acc-v1"
 220                             "qcom,kpss-acc-v2"
 221                             "renesas,apmu"
 222                             "rockchip,rk3036-smp"
 223                             "rockchip,rk3066-smp"
 224                             "ste,dbx500-smp"
 225
 226         - cpu-release-addr
 227                 Usage: required for systems that have an "enable-method"
 228                        property value of "spin-table".
 229                 Value type: <prop-encoded-array>
 230                 Definition:
 231                         # On ARM v8 64-bit systems must be a two cell
 232                           property identifying a 64-bit zero-initialised
 233                           memory location.
 234
 235         - qcom,saw
 236                 Usage: required for systems that have an "enable-method"
 237                        property value of "qcom,kpss-acc-v1" or
 238                        "qcom,kpss-acc-v2"
 239                 Value type: <phandle>
 240                 Definition: Specifies the SAW[1] node associated with this CPU.
 241
 242         - qcom,acc
 243                 Usage: required for systems that have an "enable-method"
 244                        property value of "qcom,kpss-acc-v1" or
 245                        "qcom,kpss-acc-v2"
 246                 Value type: <phandle>
 247                 Definition: Specifies the ACC[2] node associated with this CPU.
 248
 249         - cpu-idle-states
 250                 Usage: Optional
 251                 Value type: <prop-encoded-array>
 252                 Definition:
 253                         # List of phandles to idle state nodes supported
 254                           by this cpu [3].
 255
 256         - capacity-dmips-mhz
 257                 Usage: Optional
 258                 Value type: <u32>
 259                 Definition:
 260                         # u32 value representing CPU capacity [4] in
 261                           DMIPS/MHz, relative to highest capacity-dmips-mhz
 262                           in the system.
 263
 264         - rockchip,pmu
 265                 Usage: optional for systems that have an "enable-method"
 266                        property value of "rockchip,rk3066-smp"
 267                        While optional, it is the preferred way to get access to
 268                        the cpu-core power-domains.
 269                 Value type: <phandle>
 270                 Definition: Specifies the syscon node controlling the cpu core
 271                             power domains.
 272
 273         - dynamic-power-coefficient
 274                 Usage: optional
 275                 Value type: <prop-encoded-array>
 276                 Definition: A u32 value that represents the running time dynamic
 277                             power coefficient in units of mW/MHz/uV^2. The
 278                             coefficient can either be calculated from power
 279                             measurements or derived by analysis.
 280
 281                             The dynamic power consumption of the CPU  is
 282                             proportional to the square of the Voltage (V) and
 283                             the clock frequency (f). The coefficient is used to
 284                             calculate the dynamic power as below -
 285
 286                             Pdyn = dynamic-power-coefficient * V^2 * f
 287
 288                             where voltage is in uV, frequency is in MHz.
 289
 290 Example 1 (dual-cluster big.LITTLE system 32-bit):
 291
 292         cpus {
 293                 #size-cells = <0>;
 294                 #address-cells = <1>;
 295
 296                 cpu@0 {
 297                         device_type = "cpu";
 298                         compatible = "arm,cortex-a15";
 299                         reg = <0x0>;
 300                 };
 301
 302                 cpu@1 {
 303                         device_type = "cpu";
 304                         compatible = "arm,cortex-a15";
 305                         reg = <0x1>;
 306                 };
 307
 308                 cpu@100 {
 309                         device_type = "cpu";
 310                         compatible = "arm,cortex-a7";
 311                         reg = <0x100>;
 312                 };
 313
 314                 cpu@101 {
 315                         device_type = "cpu";
 316                         compatible = "arm,cortex-a7";
 317                         reg = <0x101>;
 318                 };
 319         };
 320
 321 Example 2 (Cortex-A8 uniprocessor 32-bit system):
 322
 323         cpus {
 324                 #size-cells = <0>;
 325                 #address-cells = <1>;
 326
 327                 cpu@0 {
 328                         device_type = "cpu";
 329                         compatible = "arm,cortex-a8";
 330                         reg = <0x0>;
 331                 };
 332         };
 333
 334 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 335
 336         cpus {
 337                 #size-cells = <0>;
 338                 #address-cells = <1>;
 339
 340                 cpu@0 {
 341                         device_type = "cpu";
 342                         compatible = "arm,arm926ej-s";
 343                         reg = <0x0>;
 344                 };
 345         };
 346
 347 Example 4 (ARM Cortex-A57 64-bit system):
 348
 349 cpus {
 350         #size-cells = <0>;
 351         #address-cells = <2>;
 352
 353         cpu@0 {
 354                 device_type = "cpu";
 355                 compatible = "arm,cortex-a57";
 356                 reg = <0x0 0x0>;
 357                 enable-method = "spin-table";
 358                 cpu-release-addr = <0 0x20000000>;
 359         };
 360
 361         cpu@1 {
 362                 device_type = "cpu";
 363                 compatible = "arm,cortex-a57";
 364                 reg = <0x0 0x1>;
 365                 enable-method = "spin-table";
 366                 cpu-release-addr = <0 0x20000000>;
 367         };
 368
 369         cpu@100 {
 370                 device_type = "cpu";
 371                 compatible = "arm,cortex-a57";
 372                 reg = <0x0 0x100>;
 373                 enable-method = "spin-table";
 374                 cpu-release-addr = <0 0x20000000>;
 375         };
 376
 377         cpu@101 {
 378                 device_type = "cpu";
 379                 compatible = "arm,cortex-a57";
 380                 reg = <0x0 0x101>;
 381                 enable-method = "spin-table";
 382                 cpu-release-addr = <0 0x20000000>;
 383         };
 384
 385         cpu@10000 {
 386                 device_type = "cpu";
 387                 compatible = "arm,cortex-a57";
 388                 reg = <0x0 0x10000>;
 389                 enable-method = "spin-table";
 390                 cpu-release-addr = <0 0x20000000>;
 391         };
 392
 393         cpu@10001 {
 394                 device_type = "cpu";
 395                 compatible = "arm,cortex-a57";
 396                 reg = <0x0 0x10001>;
 397                 enable-method = "spin-table";
 398                 cpu-release-addr = <0 0x20000000>;
 399         };
 400
 401         cpu@10100 {
 402                 device_type = "cpu";
 403                 compatible = "arm,cortex-a57";
 404                 reg = <0x0 0x10100>;
 405                 enable-method = "spin-table";
 406                 cpu-release-addr = <0 0x20000000>;
 407         };
 408
 409         cpu@10101 {
 410                 device_type = "cpu";
 411                 compatible = "arm,cortex-a57";
 412                 reg = <0x0 0x10101>;
 413                 enable-method = "spin-table";
 414                 cpu-release-addr = <0 0x20000000>;
 415         };
 416
 417         cpu@100000000 {
 418                 device_type = "cpu";
 419                 compatible = "arm,cortex-a57";
 420                 reg = <0x1 0x0>;
 421                 enable-method = "spin-table";
 422                 cpu-release-addr = <0 0x20000000>;
 423         };
 424
 425         cpu@100000001 {
 426                 device_type = "cpu";
 427                 compatible = "arm,cortex-a57";
 428                 reg = <0x1 0x1>;
 429                 enable-method = "spin-table";
 430                 cpu-release-addr = <0 0x20000000>;
 431         };
 432
 433         cpu@100000100 {
 434                 device_type = "cpu";
 435                 compatible = "arm,cortex-a57";
 436                 reg = <0x1 0x100>;
 437                 enable-method = "spin-table";
 438                 cpu-release-addr = <0 0x20000000>;
 439         };
 440
 441         cpu@100000101 {
 442                 device_type = "cpu";
 443                 compatible = "arm,cortex-a57";
 444                 reg = <0x1 0x101>;
 445                 enable-method = "spin-table";
 446                 cpu-release-addr = <0 0x20000000>;
 447         };
 448
 449         cpu@100010000 {
 450                 device_type = "cpu";
 451                 compatible = "arm,cortex-a57";
 452                 reg = <0x1 0x10000>;
 453                 enable-method = "spin-table";
 454                 cpu-release-addr = <0 0x20000000>;
 455         };
 456
 457         cpu@100010001 {
 458                 device_type = "cpu";
 459                 compatible = "arm,cortex-a57";
 460                 reg = <0x1 0x10001>;
 461                 enable-method = "spin-table";
 462                 cpu-release-addr = <0 0x20000000>;
 463         };
 464
 465         cpu@100010100 {
 466                 device_type = "cpu";
 467                 compatible = "arm,cortex-a57";
 468                 reg = <0x1 0x10100>;
 469                 enable-method = "spin-table";
 470                 cpu-release-addr = <0 0x20000000>;
 471         };
 472
 473         cpu@100010101 {
 474                 device_type = "cpu";
 475                 compatible = "arm,cortex-a57";
 476                 reg = <0x1 0x10101>;
 477                 enable-method = "spin-table";
 478                 cpu-release-addr = <0 0x20000000>;
 479         };
 480 };
 481
 482 --
 483 [1] arm/msm/qcom,saw2.txt
 484 [2] arm/msm/qcom,kpss-acc.txt
 485 [3] ARM Linux kernel documentation - idle states bindings
 486     Documentation/devicetree/bindings/arm/idle-states.txt
 487 [4] ARM Linux kernel documentation - cpu capacity bindings
 488     Documentation/devicetree/bindings/arm/cpu-capacity.txt