drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50 #include <drm/ttm/ttm_page_alloc.h>
  51
  52 #include <drm/drm_debugfs.h>
  53 #include <drm/amdgpu_drm.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "bif/bif_4_1_d.h"
  62
  63 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  64
  65
  66 /**
  67  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  68  * memory request.
  69  *
  70  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  71  * @type: The type of memory requested
  72  * @man: The memory type manager for each domain
  73  *
  74  * This is called by ttm_bo_init_mm() when a buffer object is being
  75  * initialized.
  76  */
  77 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  78                                 struct ttm_mem_type_manager *man)
  79 {
  80         struct amdgpu_device *adev;
  81
  82         adev = amdgpu_ttm_adev(bdev);
  83
  84         switch (type) {
  85         case TTM_PL_SYSTEM:
  86                 /* System memory */
  87                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  88                 man->available_caching = TTM_PL_MASK_CACHING;
  89                 man->default_caching = TTM_PL_FLAG_CACHED;
  90                 break;
  91         case TTM_PL_TT:
  92                 /* GTT memory  */
  93                 man->func = &amdgpu_gtt_mgr_func;
  94                 man->available_caching = TTM_PL_MASK_CACHING;
  95                 man->default_caching = TTM_PL_FLAG_CACHED;
  96                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
  97                 break;
  98         case TTM_PL_VRAM:
  99                 /* "On-card" video ram */
 100                 man->func = &amdgpu_vram_mgr_func;
 101                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 102                              TTM_MEMTYPE_FLAG_MAPPABLE;
 103                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 104                 man->default_caching = TTM_PL_FLAG_WC;
 105                 break;
 106         case AMDGPU_PL_GDS:
 107         case AMDGPU_PL_GWS:
 108         case AMDGPU_PL_OA:
 109                 /* On-chip GDS memory*/
 110                 man->func = &ttm_bo_manager_func;
 111                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 112                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 113                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 114                 break;
 115         default:
 116                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 117                 return -EINVAL;
 118         }
 119         return 0;
 120 }
 121
 122 /**
 123  * amdgpu_evict_flags - Compute placement flags
 124  *
 125  * @bo: The buffer object to evict
 126  * @placement: Possible destination(s) for evicted BO
 127  *
 128  * Fill in placement data when ttm_bo_evict() is called
 129  */
 130 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 131                                 struct ttm_placement *placement)
 132 {
 133         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 134         struct amdgpu_bo *abo;
 135         static const struct ttm_place placements = {
 136                 .fpfn = 0,
 137                 .lpfn = 0,
 138                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 139         };
 140
 141         /* Don't handle scatter gather BOs */
 142         if (bo->type == ttm_bo_type_sg) {
 143                 placement->num_placement = 0;
 144                 placement->num_busy_placement = 0;
 145                 return;
 146         }
 147
 148         /* Object isn't an AMDGPU object so ignore */
 149         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 150                 placement->placement = &placements;
 151                 placement->busy_placement = &placements;
 152                 placement->num_placement = 1;
 153                 placement->num_busy_placement = 1;
 154                 return;
 155         }
 156
 157         abo = ttm_to_amdgpu_bo(bo);
 158         switch (bo->mem.mem_type) {
 159         case AMDGPU_PL_GDS:
 160         case AMDGPU_PL_GWS:
 161         case AMDGPU_PL_OA:
 162                 placement->num_placement = 0;
 163                 placement->num_busy_placement = 0;
 164                 return;
 165
 166         case TTM_PL_VRAM:
 167                 if (!adev->mman.buffer_funcs_enabled) {
 168                         /* Move to system memory */
 169                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 170                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 171                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 172                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 173
 174                         /* Try evicting to the CPU inaccessible part of VRAM
 175                          * first, but only set GTT as busy placement, so this
 176                          * BO will be evicted to GTT rather than causing other
 177                          * BOs to be evicted from VRAM
 178                          */
 179                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 180                                                          AMDGPU_GEM_DOMAIN_GTT);
 181                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 182                         abo->placements[0].lpfn = 0;
 183                         abo->placement.busy_placement = &abo->placements[1];
 184                         abo->placement.num_busy_placement = 1;
 185                 } else {
 186                         /* Move to GTT memory */
 187                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 188                 }
 189                 break;
 190         case TTM_PL_TT:
 191         default:
 192                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 193                 break;
 194         }
 195         *placement = abo->placement;
 196 }
 197
 198 /**
 199  * amdgpu_verify_access - Verify access for a mmap call
 200  *
 201  * @bo: The buffer object to map
 202  * @filp: The file pointer from the process performing the mmap
 203  *
 204  * This is called by ttm_bo_mmap() to verify whether a process
 205  * has the right to mmap a BO to their process space.
 206  */
 207 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 208 {
 209         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 210
 211         /*
 212          * Don't verify access for KFD BOs. They don't have a GEM
 213          * object associated with them.
 214          */
 215         if (abo->kfd_bo)
 216                 return 0;
 217
 218         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 219                 return -EPERM;
 220         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 221                                           filp->private_data);
 222 }
 223
 224 /**
 225  * amdgpu_move_null - Register memory for a buffer object
 226  *
 227  * @bo: The bo to assign the memory to
 228  * @new_mem: The memory to be assigned.
 229  *
 230  * Assign the memory from new_mem to the memory of the buffer object bo.
 231  */
 232 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 233                              struct ttm_mem_reg *new_mem)
 234 {
 235         struct ttm_mem_reg *old_mem = &bo->mem;
 236
 237         BUG_ON(old_mem->mm_node != NULL);
 238         *old_mem = *new_mem;
 239         new_mem->mm_node = NULL;
 240 }
 241
 242 /**
 243  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 244  *
 245  * @bo: The bo to assign the memory to.
 246  * @mm_node: Memory manager node for drm allocator.
 247  * @mem: The region where the bo resides.
 248  *
 249  */
 250 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 251                                     struct drm_mm_node *mm_node,
 252                                     struct ttm_mem_reg *mem)
 253 {
 254         uint64_t addr = 0;
 255
 256         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 257                 addr = mm_node->start << PAGE_SHIFT;
 258                 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
 259                                                 mem->mem_type);
 260         }
 261         return addr;
 262 }
 263
 264 /**
 265  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 266  * @offset. It also modifies the offset to be within the drm_mm_node returned
 267  *
 268  * @mem: The region where the bo resides.
 269  * @offset: The offset that drm_mm_node is used for finding.
 270  *
 271  */
 272 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 273                                                uint64_t *offset)
 274 {
 275         struct drm_mm_node *mm_node = mem->mm_node;
 276
 277         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 278                 *offset -= (mm_node->size << PAGE_SHIFT);
 279                 ++mm_node;
 280         }
 281         return mm_node;
 282 }
 283
 284 /**
 285  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 286  * @bo: buffer object to map
 287  * @mem: memory object to map
 288  * @mm_node: drm_mm node object to map
 289  * @num_pages: number of pages to map
 290  * @offset: offset into @mm_node where to start
 291  * @window: which GART window to use
 292  * @ring: DMA ring to use for the copy
 293  * @tmz: if we should setup a TMZ enabled mapping
 294  * @addr: resulting address inside the MC address space
 295  *
 296  * Setup one of the GART windows to access a specific piece of memory or return
 297  * the physical address for local memory.
 298  */
 299 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 300                                  struct ttm_mem_reg *mem,
 301                                  struct drm_mm_node *mm_node,
 302                                  unsigned num_pages, uint64_t offset,
 303                                  unsigned window, struct amdgpu_ring *ring,
 304                                  bool tmz, uint64_t *addr)
 305 {
 306         struct amdgpu_device *adev = ring->adev;
 307         struct amdgpu_job *job;
 308         unsigned num_dw, num_bytes;
 309         struct dma_fence *fence;
 310         uint64_t src_addr, dst_addr;
 311         void *cpu_addr;
 312         uint64_t flags;
 313         unsigned int i;
 314         int r;
 315
 316         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 317                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 318
 319         /* Map only what can't be accessed directly */
 320         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 321                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 322                 return 0;
 323         }
 324
 325         *addr = adev->gmc.gart_start;
 326         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 327                 AMDGPU_GPU_PAGE_SIZE;
 328         *addr += offset & ~PAGE_MASK;
 329
 330         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 331         num_bytes = num_pages * 8;
 332
 333         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 334                                      AMDGPU_IB_POOL_DELAYED, &job);
 335         if (r)
 336                 return r;
 337
 338         src_addr = num_dw * 4;
 339         src_addr += job->ibs[0].gpu_addr;
 340
 341         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 342         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 343         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 344                                 dst_addr, num_bytes, false);
 345
 346         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 347         WARN_ON(job->ibs[0].length_dw > num_dw);
 348
 349         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 350         if (tmz)
 351                 flags |= AMDGPU_PTE_TMZ;
 352
 353         cpu_addr = &job->ibs[0].ptr[num_dw];
 354
 355         if (mem->mem_type == TTM_PL_TT) {
 356                 struct ttm_dma_tt *dma;
 357                 dma_addr_t *dma_address;
 358
 359                 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
 360                 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
 361                 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 362                                     cpu_addr);
 363                 if (r)
 364                         goto error_free;
 365         } else {
 366                 dma_addr_t dma_address;
 367
 368                 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
 369                 dma_address += adev->vm_manager.vram_base_offset;
 370
 371                 for (i = 0; i < num_pages; ++i) {
 372                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 373                                             &dma_address, flags, cpu_addr);
 374                         if (r)
 375                                 goto error_free;
 376
 377                         dma_address += PAGE_SIZE;
 378                 }
 379         }
 380
 381         r = amdgpu_job_submit(job, &adev->mman.entity,
 382                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 383         if (r)
 384                 goto error_free;
 385
 386         dma_fence_put(fence);
 387
 388         return r;
 389
 390 error_free:
 391         amdgpu_job_free(job);
 392         return r;
 393 }
 394
 395 /**
 396  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 397  * @adev: amdgpu device
 398  * @src: buffer/address where to read from
 399  * @dst: buffer/address where to write to
 400  * @size: number of bytes to copy
 401  * @tmz: if a secure copy should be used
 402  * @resv: resv object to sync to
 403  * @f: Returns the last fence if multiple jobs are submitted.
 404  *
 405  * The function copies @size bytes from {src->mem + src->offset} to
 406  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 407  * move and different for a BO to BO copy.
 408  *
 409  */
 410 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 411                                const struct amdgpu_copy_mem *src,
 412                                const struct amdgpu_copy_mem *dst,
 413                                uint64_t size, bool tmz,
 414                                struct dma_resv *resv,
 415                                struct dma_fence **f)
 416 {
 417         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 418                                         AMDGPU_GPU_PAGE_SIZE);
 419
 420         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 421         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 422         struct drm_mm_node *src_mm, *dst_mm;
 423         struct dma_fence *fence = NULL;
 424         int r = 0;
 425
 426         if (!adev->mman.buffer_funcs_enabled) {
 427                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 428                 return -EINVAL;
 429         }
 430
 431         src_offset = src->offset;
 432         src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 433         src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 434
 435         dst_offset = dst->offset;
 436         dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 437         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 438
 439         mutex_lock(&adev->mman.gtt_window_lock);
 440
 441         while (size) {
 442                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 443                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 444                 struct dma_fence *next;
 445                 uint32_t cur_size;
 446                 uint64_t from, to;
 447
 448                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 449                  * begins at an offset, then adjust the size accordingly
 450                  */
 451                 cur_size = max(src_page_offset, dst_page_offset);
 452                 cur_size = min(min3(src_node_size, dst_node_size, size),
 453                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 454
 455                 /* Map src to window 0 and dst to window 1. */
 456                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 457                                           PFN_UP(cur_size + src_page_offset),
 458                                           src_offset, 0, ring, tmz, &from);
 459                 if (r)
 460                         goto error;
 461
 462                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 463                                           PFN_UP(cur_size + dst_page_offset),
 464                                           dst_offset, 1, ring, tmz, &to);
 465                 if (r)
 466                         goto error;
 467
 468                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 469                                        resv, &next, false, true, tmz);
 470                 if (r)
 471                         goto error;
 472
 473                 dma_fence_put(fence);
 474                 fence = next;
 475
 476                 size -= cur_size;
 477                 if (!size)
 478                         break;
 479
 480                 src_node_size -= cur_size;
 481                 if (!src_node_size) {
 482                         ++src_mm;
 483                         src_node_size = src_mm->size << PAGE_SHIFT;
 484                         src_offset = 0;
 485                 } else {
 486                         src_offset += cur_size;
 487                 }
 488
 489                 dst_node_size -= cur_size;
 490                 if (!dst_node_size) {
 491                         ++dst_mm;
 492                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 493                         dst_offset = 0;
 494                 } else {
 495                         dst_offset += cur_size;
 496                 }
 497         }
 498 error:
 499         mutex_unlock(&adev->mman.gtt_window_lock);
 500         if (f)
 501                 *f = dma_fence_get(fence);
 502         dma_fence_put(fence);
 503         return r;
 504 }
 505
 506 /**
 507  * amdgpu_move_blit - Copy an entire buffer to another buffer
 508  *
 509  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 510  * help move buffers to and from VRAM.
 511  */
 512 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 513                             bool evict, bool no_wait_gpu,
 514                             struct ttm_mem_reg *new_mem,
 515                             struct ttm_mem_reg *old_mem)
 516 {
 517         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 518         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 519         struct amdgpu_copy_mem src, dst;
 520         struct dma_fence *fence = NULL;
 521         int r;
 522
 523         src.bo = bo;
 524         dst.bo = bo;
 525         src.mem = old_mem;
 526         dst.mem = new_mem;
 527         src.offset = 0;
 528         dst.offset = 0;
 529
 530         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 531                                        new_mem->num_pages << PAGE_SHIFT,
 532                                        amdgpu_bo_encrypted(abo),
 533                                        bo->base.resv, &fence);
 534         if (r)
 535                 goto error;
 536
 537         /* clear the space being freed */
 538         if (old_mem->mem_type == TTM_PL_VRAM &&
 539             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 540                 struct dma_fence *wipe_fence = NULL;
 541
 542                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 543                                        NULL, &wipe_fence);
 544                 if (r) {
 545                         goto error;
 546                 } else if (wipe_fence) {
 547                         dma_fence_put(fence);
 548                         fence = wipe_fence;
 549                 }
 550         }
 551
 552         /* Always block for VM page tables before committing the new location */
 553         if (bo->type == ttm_bo_type_kernel)
 554                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 555         else
 556                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 557         dma_fence_put(fence);
 558         return r;
 559
 560 error:
 561         if (fence)
 562                 dma_fence_wait(fence, false);
 563         dma_fence_put(fence);
 564         return r;
 565 }
 566
 567 /**
 568  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 569  *
 570  * Called by amdgpu_bo_move().
 571  */
 572 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 573                                 struct ttm_operation_ctx *ctx,
 574                                 struct ttm_mem_reg *new_mem)
 575 {
 576         struct ttm_mem_reg *old_mem = &bo->mem;
 577         struct ttm_mem_reg tmp_mem;
 578         struct ttm_place placements;
 579         struct ttm_placement placement;
 580         int r;
 581
 582         /* create space/pages for new_mem in GTT space */
 583         tmp_mem = *new_mem;
 584         tmp_mem.mm_node = NULL;
 585         placement.num_placement = 1;
 586         placement.placement = &placements;
 587         placement.num_busy_placement = 1;
 588         placement.busy_placement = &placements;
 589         placements.fpfn = 0;
 590         placements.lpfn = 0;
 591         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 592         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 593         if (unlikely(r)) {
 594                 pr_err("Failed to find GTT space for blit from VRAM\n");
 595                 return r;
 596         }
 597
 598         /* set caching flags */
 599         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 600         if (unlikely(r)) {
 601                 goto out_cleanup;
 602         }
 603
 604         /* Bind the memory to the GTT space */
 605         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 606         if (unlikely(r)) {
 607                 goto out_cleanup;
 608         }
 609
 610         /* blit VRAM to GTT */
 611         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 612         if (unlikely(r)) {
 613                 goto out_cleanup;
 614         }
 615
 616         /* move BO (in tmp_mem) to new_mem */
 617         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 618 out_cleanup:
 619         ttm_bo_mem_put(bo, &tmp_mem);
 620         return r;
 621 }
 622
 623 /**
 624  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 625  *
 626  * Called by amdgpu_bo_move().
 627  */
 628 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 629                                 struct ttm_operation_ctx *ctx,
 630                                 struct ttm_mem_reg *new_mem)
 631 {
 632         struct ttm_mem_reg *old_mem = &bo->mem;
 633         struct ttm_mem_reg tmp_mem;
 634         struct ttm_placement placement;
 635         struct ttm_place placements;
 636         int r;
 637
 638         /* make space in GTT for old_mem buffer */
 639         tmp_mem = *new_mem;
 640         tmp_mem.mm_node = NULL;
 641         placement.num_placement = 1;
 642         placement.placement = &placements;
 643         placement.num_busy_placement = 1;
 644         placement.busy_placement = &placements;
 645         placements.fpfn = 0;
 646         placements.lpfn = 0;
 647         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 648         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 649         if (unlikely(r)) {
 650                 pr_err("Failed to find GTT space for blit to VRAM\n");
 651                 return r;
 652         }
 653
 654         /* move/bind old memory to GTT space */
 655         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 656         if (unlikely(r)) {
 657                 goto out_cleanup;
 658         }
 659
 660         /* copy to VRAM */
 661         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 662         if (unlikely(r)) {
 663                 goto out_cleanup;
 664         }
 665 out_cleanup:
 666         ttm_bo_mem_put(bo, &tmp_mem);
 667         return r;
 668 }
 669
 670 /**
 671  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 672  *
 673  * Called by amdgpu_bo_move()
 674  */
 675 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 676                                struct ttm_mem_reg *mem)
 677 {
 678         struct drm_mm_node *nodes = mem->mm_node;
 679
 680         if (mem->mem_type == TTM_PL_SYSTEM ||
 681             mem->mem_type == TTM_PL_TT)
 682                 return true;
 683         if (mem->mem_type != TTM_PL_VRAM)
 684                 return false;
 685
 686         /* ttm_mem_reg_ioremap only supports contiguous memory */
 687         if (nodes->size != mem->num_pages)
 688                 return false;
 689
 690         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 691                 <= adev->gmc.visible_vram_size;
 692 }
 693
 694 /**
 695  * amdgpu_bo_move - Move a buffer object to a new memory location
 696  *
 697  * Called by ttm_bo_handle_move_mem()
 698  */
 699 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 700                           struct ttm_operation_ctx *ctx,
 701                           struct ttm_mem_reg *new_mem)
 702 {
 703         struct amdgpu_device *adev;
 704         struct amdgpu_bo *abo;
 705         struct ttm_mem_reg *old_mem = &bo->mem;
 706         int r;
 707
 708         /* Can't move a pinned BO */
 709         abo = ttm_to_amdgpu_bo(bo);
 710         if (WARN_ON_ONCE(abo->pin_count > 0))
 711                 return -EINVAL;
 712
 713         adev = amdgpu_ttm_adev(bo->bdev);
 714
 715         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 716                 amdgpu_move_null(bo, new_mem);
 717                 return 0;
 718         }
 719         if ((old_mem->mem_type == TTM_PL_TT &&
 720              new_mem->mem_type == TTM_PL_SYSTEM) ||
 721             (old_mem->mem_type == TTM_PL_SYSTEM &&
 722              new_mem->mem_type == TTM_PL_TT)) {
 723                 /* bind is enough */
 724                 amdgpu_move_null(bo, new_mem);
 725                 return 0;
 726         }
 727         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 728             old_mem->mem_type == AMDGPU_PL_GWS ||
 729             old_mem->mem_type == AMDGPU_PL_OA ||
 730             new_mem->mem_type == AMDGPU_PL_GDS ||
 731             new_mem->mem_type == AMDGPU_PL_GWS ||
 732             new_mem->mem_type == AMDGPU_PL_OA) {
 733                 /* Nothing to save here */
 734                 amdgpu_move_null(bo, new_mem);
 735                 return 0;
 736         }
 737
 738         if (!adev->mman.buffer_funcs_enabled) {
 739                 r = -ENODEV;
 740                 goto memcpy;
 741         }
 742
 743         if (old_mem->mem_type == TTM_PL_VRAM &&
 744             new_mem->mem_type == TTM_PL_SYSTEM) {
 745                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 746         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 747                    new_mem->mem_type == TTM_PL_VRAM) {
 748                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 749         } else {
 750                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 751                                      new_mem, old_mem);
 752         }
 753
 754         if (r) {
 755 memcpy:
 756                 /* Check that all memory is CPU accessible */
 757                 if (!amdgpu_mem_visible(adev, old_mem) ||
 758                     !amdgpu_mem_visible(adev, new_mem)) {
 759                         pr_err("Move buffer fallback to memcpy unavailable\n");
 760                         return r;
 761                 }
 762
 763                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 764                 if (r)
 765                         return r;
 766         }
 767
 768         if (bo->type == ttm_bo_type_device &&
 769             new_mem->mem_type == TTM_PL_VRAM &&
 770             old_mem->mem_type != TTM_PL_VRAM) {
 771                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 772                  * accesses the BO after it's moved.
 773                  */
 774                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 775         }
 776
 777         /* update statistics */
 778         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 779         return 0;
 780 }
 781
 782 /**
 783  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 784  *
 785  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 786  */
 787 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 788 {
 789         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 790         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 791         struct drm_mm_node *mm_node = mem->mm_node;
 792
 793         mem->bus.addr = NULL;
 794         mem->bus.offset = 0;
 795         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 796         mem->bus.base = 0;
 797         mem->bus.is_iomem = false;
 798         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 799                 return -EINVAL;
 800         switch (mem->mem_type) {
 801         case TTM_PL_SYSTEM:
 802                 /* system memory */
 803                 return 0;
 804         case TTM_PL_TT:
 805                 break;
 806         case TTM_PL_VRAM:
 807                 mem->bus.offset = mem->start << PAGE_SHIFT;
 808                 /* check if it's visible */
 809                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 810                         return -EINVAL;
 811                 /* Only physically contiguous buffers apply. In a contiguous
 812                  * buffer, size of the first mm_node would match the number of
 813                  * pages in ttm_mem_reg.
 814                  */
 815                 if (adev->mman.aper_base_kaddr &&
 816                     (mm_node->size == mem->num_pages))
 817                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 818                                         mem->bus.offset;
 819
 820                 mem->bus.base = adev->gmc.aper_base;
 821                 mem->bus.is_iomem = true;
 822                 break;
 823         default:
 824                 return -EINVAL;
 825         }
 826         return 0;
 827 }
 828
 829 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 830 {
 831 }
 832
 833 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 834                                            unsigned long page_offset)
 835 {
 836         uint64_t offset = (page_offset << PAGE_SHIFT);
 837         struct drm_mm_node *mm;
 838
 839         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 840         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 841                 (offset >> PAGE_SHIFT);
 842 }
 843
 844 /**
 845  * amdgpu_ttm_domain_start - Returns GPU start address
 846  * @adev: amdgpu device object
 847  * @type: type of the memory
 848  *
 849  * Returns:
 850  * GPU start address of a memory domain
 851  */
 852
 853 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 854 {
 855         switch (type) {
 856         case TTM_PL_TT:
 857                 return adev->gmc.gart_start;
 858         case TTM_PL_VRAM:
 859                 return adev->gmc.vram_start;
 860         }
 861
 862         return 0;
 863 }
 864
 865 /*
 866  * TTM backend functions.
 867  */
 868 struct amdgpu_ttm_tt {
 869         struct ttm_dma_tt       ttm;
 870         struct drm_gem_object   *gobj;
 871         u64                     offset;
 872         uint64_t                userptr;
 873         struct task_struct      *usertask;
 874         uint32_t                userflags;
 875 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 876         struct hmm_range        *range;
 877 #endif
 878 };
 879
 880 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 881 /**
 882  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 883  * memory and start HMM tracking CPU page table update
 884  *
 885  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 886  * once afterwards to stop HMM tracking
 887  */
 888 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 889 {
 890         struct ttm_tt *ttm = bo->tbo.ttm;
 891         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 892         unsigned long start = gtt->userptr;
 893         struct vm_area_struct *vma;
 894         struct hmm_range *range;
 895         unsigned long timeout;
 896         struct mm_struct *mm;
 897         unsigned long i;
 898         int r = 0;
 899
 900         mm = bo->notifier.mm;
 901         if (unlikely(!mm)) {
 902                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 903                 return -EFAULT;
 904         }
 905
 906         /* Another get_user_pages is running at the same time?? */
 907         if (WARN_ON(gtt->range))
 908                 return -EFAULT;
 909
 910         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 911                 return -ESRCH;
 912
 913         range = kzalloc(sizeof(*range), GFP_KERNEL);
 914         if (unlikely(!range)) {
 915                 r = -ENOMEM;
 916                 goto out;
 917         }
 918         range->notifier = &bo->notifier;
 919         range->start = bo->notifier.interval_tree.start;
 920         range->end = bo->notifier.interval_tree.last + 1;
 921         range->default_flags = HMM_PFN_REQ_FAULT;
 922         if (!amdgpu_ttm_tt_is_readonly(ttm))
 923                 range->default_flags |= HMM_PFN_REQ_WRITE;
 924
 925         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 926                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 927         if (unlikely(!range->hmm_pfns)) {
 928                 r = -ENOMEM;
 929                 goto out_free_ranges;
 930         }
 931
 932         mmap_read_lock(mm);
 933         vma = find_vma(mm, start);
 934         if (unlikely(!vma || start < vma->vm_start)) {
 935                 r = -EFAULT;
 936                 goto out_unlock;
 937         }
 938         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 939                 vma->vm_file)) {
 940                 r = -EPERM;
 941                 goto out_unlock;
 942         }
 943         mmap_read_unlock(mm);
 944         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 945
 946 retry:
 947         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 948
 949         mmap_read_lock(mm);
 950         r = hmm_range_fault(range);
 951         mmap_read_unlock(mm);
 952         if (unlikely(r)) {
 953                 /*
 954                  * FIXME: This timeout should encompass the retry from
 955                  * mmu_interval_read_retry() as well.
 956                  */
 957                 if (r == -EBUSY && !time_after(jiffies, timeout))
 958                         goto retry;
 959                 goto out_free_pfns;
 960         }
 961
 962         /*
 963          * Due to default_flags, all pages are HMM_PFN_VALID or
 964          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 965          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 966          */
 967         for (i = 0; i < ttm->num_pages; i++)
 968                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 969
 970         gtt->range = range;
 971         mmput(mm);
 972
 973         return 0;
 974
 975 out_unlock:
 976         mmap_read_unlock(mm);
 977 out_free_pfns:
 978         kvfree(range->hmm_pfns);
 979 out_free_ranges:
 980         kfree(range);
 981 out:
 982         mmput(mm);
 983         return r;
 984 }
 985
 986 /**
 987  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 988  * Check if the pages backing this ttm range have been invalidated
 989  *
 990  * Returns: true if pages are still valid
 991  */
 992 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 993 {
 994         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 995         bool r = false;
 996
 997         if (!gtt || !gtt->userptr)
 998                 return false;
 999
1000         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
1001                 gtt->userptr, ttm->num_pages);
1002
1003         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
1004                 "No user pages to check\n");
1005
1006         if (gtt->range) {
1007                 /*
1008                  * FIXME: Must always hold notifier_lock for this, and must
1009                  * not ignore the return code.
1010                  */
1011                 r = mmu_interval_read_retry(gtt->range->notifier,
1012                                          gtt->range->notifier_seq);
1013                 kvfree(gtt->range->hmm_pfns);
1014                 kfree(gtt->range);
1015                 gtt->range = NULL;
1016         }
1017
1018         return !r;
1019 }
1020 #endif
1021
1022 /**
1023  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
1024  *
1025  * Called by amdgpu_cs_list_validate(). This creates the page list
1026  * that backs user memory and will ultimately be mapped into the device
1027  * address space.
1028  */
1029 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
1030 {
1031         unsigned long i;
1032
1033         for (i = 0; i < ttm->num_pages; ++i)
1034                 ttm->pages[i] = pages ? pages[i] : NULL;
1035 }
1036
1037 /**
1038  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
1039  *
1040  * Called by amdgpu_ttm_backend_bind()
1041  **/
1042 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
1043 {
1044         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1045         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1046         unsigned nents;
1047         int r;
1048
1049         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1050         enum dma_data_direction direction = write ?
1051                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1052
1053         /* Allocate an SG array and squash pages into it */
1054         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1055                                       ttm->num_pages << PAGE_SHIFT,
1056                                       GFP_KERNEL);
1057         if (r)
1058                 goto release_sg;
1059
1060         /* Map SG to device */
1061         r = -ENOMEM;
1062         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
1063         if (nents == 0)
1064                 goto release_sg;
1065
1066         /* convert SG to linear array of pages and dma addresses */
1067         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1068                                          gtt->ttm.dma_address, ttm->num_pages);
1069
1070         return 0;
1071
1072 release_sg:
1073         kfree(ttm->sg);
1074         return r;
1075 }
1076
1077 /**
1078  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1079  */
1080 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
1081 {
1082         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1083         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1084
1085         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1086         enum dma_data_direction direction = write ?
1087                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1088
1089         /* double check that we don't free the table twice */
1090         if (!ttm->sg->sgl)
1091                 return;
1092
1093         /* unmap the pages mapped to the device */
1094         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
1095
1096         sg_free_table(ttm->sg);
1097
1098 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1099         if (gtt->range) {
1100                 unsigned long i;
1101
1102                 for (i = 0; i < ttm->num_pages; i++) {
1103                         if (ttm->pages[i] !=
1104                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1105                                 break;
1106                 }
1107
1108                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1109         }
1110 #endif
1111 }
1112
1113 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1114                                 struct ttm_buffer_object *tbo,
1115                                 uint64_t flags)
1116 {
1117         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1118         struct ttm_tt *ttm = tbo->ttm;
1119         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1120         int r;
1121
1122         if (amdgpu_bo_encrypted(abo))
1123                 flags |= AMDGPU_PTE_TMZ;
1124
1125         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1126                 uint64_t page_idx = 1;
1127
1128                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1129                                 ttm->pages, gtt->ttm.dma_address, flags);
1130                 if (r)
1131                         goto gart_bind_fail;
1132
1133                 /* The memory type of the first page defaults to UC. Now
1134                  * modify the memory type to NC from the second page of
1135                  * the BO onward.
1136                  */
1137                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1138                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1139
1140                 r = amdgpu_gart_bind(adev,
1141                                 gtt->offset + (page_idx << PAGE_SHIFT),
1142                                 ttm->num_pages - page_idx,
1143                                 &ttm->pages[page_idx],
1144                                 &(gtt->ttm.dma_address[page_idx]), flags);
1145         } else {
1146                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1147                                      ttm->pages, gtt->ttm.dma_address, flags);
1148         }
1149
1150 gart_bind_fail:
1151         if (r)
1152                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1153                           ttm->num_pages, gtt->offset);
1154
1155         return r;
1156 }
1157
1158 /**
1159  * amdgpu_ttm_backend_bind - Bind GTT memory
1160  *
1161  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1162  * This handles binding GTT memory to the device address space.
1163  */
1164 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1165                                    struct ttm_mem_reg *bo_mem)
1166 {
1167         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1168         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1169         uint64_t flags;
1170         int r = 0;
1171
1172         if (gtt->userptr) {
1173                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1174                 if (r) {
1175                         DRM_ERROR("failed to pin userptr\n");
1176                         return r;
1177                 }
1178         }
1179         if (!ttm->num_pages) {
1180                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1181                      ttm->num_pages, bo_mem, ttm);
1182         }
1183
1184         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1185             bo_mem->mem_type == AMDGPU_PL_GWS ||
1186             bo_mem->mem_type == AMDGPU_PL_OA)
1187                 return -EINVAL;
1188
1189         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1190                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1191                 return 0;
1192         }
1193
1194         /* compute PTE flags relevant to this BO memory */
1195         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1196
1197         /* bind pages into GART page tables */
1198         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1199         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1200                 ttm->pages, gtt->ttm.dma_address, flags);
1201
1202         if (r)
1203                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1204                           ttm->num_pages, gtt->offset);
1205         return r;
1206 }
1207
1208 /**
1209  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1210  */
1211 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1212 {
1213         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1214         struct ttm_operation_ctx ctx = { false, false };
1215         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1216         struct ttm_mem_reg tmp;
1217         struct ttm_placement placement;
1218         struct ttm_place placements;
1219         uint64_t addr, flags;
1220         int r;
1221
1222         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1223                 return 0;
1224
1225         addr = amdgpu_gmc_agp_addr(bo);
1226         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1227                 bo->mem.start = addr >> PAGE_SHIFT;
1228         } else {
1229
1230                 /* allocate GART space */
1231                 tmp = bo->mem;
1232                 tmp.mm_node = NULL;
1233                 placement.num_placement = 1;
1234                 placement.placement = &placements;
1235                 placement.num_busy_placement = 1;
1236                 placement.busy_placement = &placements;
1237                 placements.fpfn = 0;
1238                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1239                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1240                         TTM_PL_FLAG_TT;
1241
1242                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1243                 if (unlikely(r))
1244                         return r;
1245
1246                 /* compute PTE flags for this buffer object */
1247                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1248
1249                 /* Bind pages */
1250                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1251                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1252                 if (unlikely(r)) {
1253                         ttm_bo_mem_put(bo, &tmp);
1254                         return r;
1255                 }
1256
1257                 ttm_bo_mem_put(bo, &bo->mem);
1258                 bo->mem = tmp;
1259         }
1260
1261         return 0;
1262 }
1263
1264 /**
1265  * amdgpu_ttm_recover_gart - Rebind GTT pages
1266  *
1267  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1268  * rebind GTT pages during a GPU reset.
1269  */
1270 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1271 {
1272         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1273         uint64_t flags;
1274         int r;
1275
1276         if (!tbo->ttm)
1277                 return 0;
1278
1279         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1280         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1281
1282         return r;
1283 }
1284
1285 /**
1286  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1287  *
1288  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1289  * ttm_tt_destroy().
1290  */
1291 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1292 {
1293         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1294         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1295         int r;
1296
1297         /* if the pages have userptr pinning then clear that first */
1298         if (gtt->userptr)
1299                 amdgpu_ttm_tt_unpin_userptr(ttm);
1300
1301         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1302                 return 0;
1303
1304         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1305         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1306         if (r)
1307                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1308                           gtt->ttm.ttm.num_pages, gtt->offset);
1309         return r;
1310 }
1311
1312 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1313 {
1314         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1315
1316         if (gtt->usertask)
1317                 put_task_struct(gtt->usertask);
1318
1319         ttm_dma_tt_fini(&gtt->ttm);
1320         kfree(gtt);
1321 }
1322
1323 static struct ttm_backend_func amdgpu_backend_func = {
1324         .bind = &amdgpu_ttm_backend_bind,
1325         .unbind = &amdgpu_ttm_backend_unbind,
1326         .destroy = &amdgpu_ttm_backend_destroy,
1327 };
1328
1329 /**
1330  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1331  *
1332  * @bo: The buffer object to create a GTT ttm_tt object around
1333  *
1334  * Called by ttm_tt_create().
1335  */
1336 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1337                                            uint32_t page_flags)
1338 {
1339         struct amdgpu_ttm_tt *gtt;
1340
1341         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1342         if (gtt == NULL) {
1343                 return NULL;
1344         }
1345         gtt->ttm.ttm.func = &amdgpu_backend_func;
1346         gtt->gobj = &bo->base;
1347
1348         /* allocate space for the uninitialized page entries */
1349         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1350                 kfree(gtt);
1351                 return NULL;
1352         }
1353         return &gtt->ttm.ttm;
1354 }
1355
1356 /**
1357  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1358  *
1359  * Map the pages of a ttm_tt object to an address space visible
1360  * to the underlying device.
1361  */
1362 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1363                         struct ttm_operation_ctx *ctx)
1364 {
1365         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1366         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1367
1368         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1369         if (gtt && gtt->userptr) {
1370                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1371                 if (!ttm->sg)
1372                         return -ENOMEM;
1373
1374                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1375                 ttm->state = tt_unbound;
1376                 return 0;
1377         }
1378
1379         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1380                 if (!ttm->sg) {
1381                         struct dma_buf_attachment *attach;
1382                         struct sg_table *sgt;
1383
1384                         attach = gtt->gobj->import_attach;
1385                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1386                         if (IS_ERR(sgt))
1387                                 return PTR_ERR(sgt);
1388
1389                         ttm->sg = sgt;
1390                 }
1391
1392                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1393                                                  gtt->ttm.dma_address,
1394                                                  ttm->num_pages);
1395                 ttm->state = tt_unbound;
1396                 return 0;
1397         }
1398
1399 #ifdef CONFIG_SWIOTLB
1400         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1401                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1402         }
1403 #endif
1404
1405         /* fall back to generic helper to populate the page array
1406          * and map them to the device */
1407         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1408 }
1409
1410 /**
1411  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1412  *
1413  * Unmaps pages of a ttm_tt object from the device address space and
1414  * unpopulates the page array backing it.
1415  */
1416 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1417 {
1418         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1419         struct amdgpu_device *adev;
1420
1421         if (gtt && gtt->userptr) {
1422                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1423                 kfree(ttm->sg);
1424                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1425                 return;
1426         }
1427
1428         if (ttm->sg && gtt->gobj->import_attach) {
1429                 struct dma_buf_attachment *attach;
1430
1431                 attach = gtt->gobj->import_attach;
1432                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1433                 ttm->sg = NULL;
1434                 return;
1435         }
1436
1437         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1438                 return;
1439
1440         adev = amdgpu_ttm_adev(ttm->bdev);
1441
1442 #ifdef CONFIG_SWIOTLB
1443         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1444                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1445                 return;
1446         }
1447 #endif
1448
1449         /* fall back to generic helper to unmap and unpopulate array */
1450         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1451 }
1452
1453 /**
1454  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1455  * task
1456  *
1457  * @ttm: The ttm_tt object to bind this userptr object to
1458  * @addr:  The address in the current tasks VM space to use
1459  * @flags: Requirements of userptr object.
1460  *
1461  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1462  * to current task
1463  */
1464 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1465                               uint32_t flags)
1466 {
1467         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1468
1469         if (gtt == NULL)
1470                 return -EINVAL;
1471
1472         gtt->userptr = addr;
1473         gtt->userflags = flags;
1474
1475         if (gtt->usertask)
1476                 put_task_struct(gtt->usertask);
1477         gtt->usertask = current->group_leader;
1478         get_task_struct(gtt->usertask);
1479
1480         return 0;
1481 }
1482
1483 /**
1484  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1485  */
1486 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1487 {
1488         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1489
1490         if (gtt == NULL)
1491                 return NULL;
1492
1493         if (gtt->usertask == NULL)
1494                 return NULL;
1495
1496         return gtt->usertask->mm;
1497 }
1498
1499 /**
1500  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1501  * address range for the current task.
1502  *
1503  */
1504 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1505                                   unsigned long end)
1506 {
1507         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1508         unsigned long size;
1509
1510         if (gtt == NULL || !gtt->userptr)
1511                 return false;
1512
1513         /* Return false if no part of the ttm_tt object lies within
1514          * the range
1515          */
1516         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1517         if (gtt->userptr > end || gtt->userptr + size <= start)
1518                 return false;
1519
1520         return true;
1521 }
1522
1523 /**
1524  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1525  */
1526 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1527 {
1528         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1529
1530         if (gtt == NULL || !gtt->userptr)
1531                 return false;
1532
1533         return true;
1534 }
1535
1536 /**
1537  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1538  */
1539 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1540 {
1541         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1542
1543         if (gtt == NULL)
1544                 return false;
1545
1546         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1547 }
1548
1549 /**
1550  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1551  *
1552  * @ttm: The ttm_tt object to compute the flags for
1553  * @mem: The memory registry backing this ttm_tt object
1554  *
1555  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1556  */
1557 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1558 {
1559         uint64_t flags = 0;
1560
1561         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1562                 flags |= AMDGPU_PTE_VALID;
1563
1564         if (mem && mem->mem_type == TTM_PL_TT) {
1565                 flags |= AMDGPU_PTE_SYSTEM;
1566
1567                 if (ttm->caching_state == tt_cached)
1568                         flags |= AMDGPU_PTE_SNOOPED;
1569         }
1570
1571         return flags;
1572 }
1573
1574 /**
1575  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1576  *
1577  * @ttm: The ttm_tt object to compute the flags for
1578  * @mem: The memory registry backing this ttm_tt object
1579
1580  * Figure out the flags to use for a VM PTE (Page Table Entry).
1581  */
1582 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1583                                  struct ttm_mem_reg *mem)
1584 {
1585         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1586
1587         flags |= adev->gart.gart_pte_flags;
1588         flags |= AMDGPU_PTE_READABLE;
1589
1590         if (!amdgpu_ttm_tt_is_readonly(ttm))
1591                 flags |= AMDGPU_PTE_WRITEABLE;
1592
1593         return flags;
1594 }
1595
1596 /**
1597  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1598  * object.
1599  *
1600  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1601  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1602  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1603  * used to clean out a memory space.
1604  */
1605 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1606                                             const struct ttm_place *place)
1607 {
1608         unsigned long num_pages = bo->mem.num_pages;
1609         struct drm_mm_node *node = bo->mem.mm_node;
1610         struct dma_resv_list *flist;
1611         struct dma_fence *f;
1612         int i;
1613
1614         if (bo->type == ttm_bo_type_kernel &&
1615             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1616                 return false;
1617
1618         /* If bo is a KFD BO, check if the bo belongs to the current process.
1619          * If true, then return false as any KFD process needs all its BOs to
1620          * be resident to run successfully
1621          */
1622         flist = dma_resv_get_list(bo->base.resv);
1623         if (flist) {
1624                 for (i = 0; i < flist->shared_count; ++i) {
1625                         f = rcu_dereference_protected(flist->shared[i],
1626                                 dma_resv_held(bo->base.resv));
1627                         if (amdkfd_fence_check_mm(f, current->mm))
1628                                 return false;
1629                 }
1630         }
1631
1632         switch (bo->mem.mem_type) {
1633         case TTM_PL_TT:
1634                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1635                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1636                         return false;
1637                 return true;
1638
1639         case TTM_PL_VRAM:
1640                 /* Check each drm MM node individually */
1641                 while (num_pages) {
1642                         if (place->fpfn < (node->start + node->size) &&
1643                             !(place->lpfn && place->lpfn <= node->start))
1644                                 return true;
1645
1646                         num_pages -= node->size;
1647                         ++node;
1648                 }
1649                 return false;
1650
1651         default:
1652                 break;
1653         }
1654
1655         return ttm_bo_eviction_valuable(bo, place);
1656 }
1657
1658 /**
1659  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1660  *
1661  * @bo:  The buffer object to read/write
1662  * @offset:  Offset into buffer object
1663  * @buf:  Secondary buffer to write/read from
1664  * @len: Length in bytes of access
1665  * @write:  true if writing
1666  *
1667  * This is used to access VRAM that backs a buffer object via MMIO
1668  * access for debugging purposes.
1669  */
1670 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1671                                     unsigned long offset,
1672                                     void *buf, int len, int write)
1673 {
1674         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1675         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1676         struct drm_mm_node *nodes;
1677         uint32_t value = 0;
1678         int ret = 0;
1679         uint64_t pos;
1680         unsigned long flags;
1681
1682         if (bo->mem.mem_type != TTM_PL_VRAM)
1683                 return -EIO;
1684
1685         pos = offset;
1686         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1687         pos += (nodes->start << PAGE_SHIFT);
1688
1689         while (len && pos < adev->gmc.mc_vram_size) {
1690                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1691                 uint64_t bytes = 4 - (pos & 3);
1692                 uint32_t shift = (pos & 3) * 8;
1693                 uint32_t mask = 0xffffffff << shift;
1694
1695                 if (len < bytes) {
1696                         mask &= 0xffffffff >> (bytes - len) * 8;
1697                         bytes = len;
1698                 }
1699
1700                 if (mask != 0xffffffff) {
1701                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1702                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1703                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1704                         if (!write || mask != 0xffffffff)
1705                                 value = RREG32_NO_KIQ(mmMM_DATA);
1706                         if (write) {
1707                                 value &= ~mask;
1708                                 value |= (*(uint32_t *)buf << shift) & mask;
1709                                 WREG32_NO_KIQ(mmMM_DATA, value);
1710                         }
1711                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1712                         if (!write) {
1713                                 value = (value & mask) >> shift;
1714                                 memcpy(buf, &value, bytes);
1715                         }
1716                 } else {
1717                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1718                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1719
1720                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1721                                                   bytes, write);
1722                 }
1723
1724                 ret += bytes;
1725                 buf = (uint8_t *)buf + bytes;
1726                 pos += bytes;
1727                 len -= bytes;
1728                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1729                         ++nodes;
1730                         pos = (nodes->start << PAGE_SHIFT);
1731                 }
1732         }
1733
1734         return ret;
1735 }
1736
1737 static struct ttm_bo_driver amdgpu_bo_driver = {
1738         .ttm_tt_create = &amdgpu_ttm_tt_create,
1739         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1740         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1741         .init_mem_type = &amdgpu_init_mem_type,
1742         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1743         .evict_flags = &amdgpu_evict_flags,
1744         .move = &amdgpu_bo_move,
1745         .verify_access = &amdgpu_verify_access,
1746         .move_notify = &amdgpu_bo_move_notify,
1747         .release_notify = &amdgpu_bo_release_notify,
1748         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1749         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1750         .io_mem_free = &amdgpu_ttm_io_mem_free,
1751         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1752         .access_memory = &amdgpu_ttm_access_memory,
1753         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1754 };
1755
1756 /*
1757  * Firmware Reservation functions
1758  */
1759 /**
1760  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1761  *
1762  * @adev: amdgpu_device pointer
1763  *
1764  * free fw reserved vram if it has been reserved.
1765  */
1766 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1767 {
1768         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1769                 NULL, &adev->fw_vram_usage.va);
1770 }
1771
1772 /**
1773  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1774  *
1775  * @adev: amdgpu_device pointer
1776  *
1777  * create bo vram reservation from fw.
1778  */
1779 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1780 {
1781         uint64_t vram_size = adev->gmc.visible_vram_size;
1782
1783         adev->fw_vram_usage.va = NULL;
1784         adev->fw_vram_usage.reserved_bo = NULL;
1785
1786         if (adev->fw_vram_usage.size == 0 ||
1787             adev->fw_vram_usage.size > vram_size)
1788                 return 0;
1789
1790         return amdgpu_bo_create_kernel_at(adev,
1791                                           adev->fw_vram_usage.start_offset,
1792                                           adev->fw_vram_usage.size,
1793                                           AMDGPU_GEM_DOMAIN_VRAM,
1794                                           &adev->fw_vram_usage.reserved_bo,
1795                                           &adev->fw_vram_usage.va);
1796 }
1797
1798 /*
1799  * Memoy training reservation functions
1800  */
1801
1802 /**
1803  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1804  *
1805  * @adev: amdgpu_device pointer
1806  *
1807  * free memory training reserved vram if it has been reserved.
1808  */
1809 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1810 {
1811         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1812
1813         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1814         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1815         ctx->c2p_bo = NULL;
1816
1817         return 0;
1818 }
1819
1820 static u64 amdgpu_ttm_training_get_c2p_offset(u64 vram_size)
1821 {
1822        if ((vram_size & (SZ_1M - 1)) < (SZ_4K + 1) )
1823                vram_size -= SZ_1M;
1824
1825        return ALIGN(vram_size, SZ_1M);
1826 }
1827
1828 /**
1829  * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
1830  *
1831  * @adev: amdgpu_device pointer
1832  *
1833  * create bo vram reservation from memory training.
1834  */
1835 static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
1836 {
1837         int ret;
1838         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1839
1840         memset(ctx, 0, sizeof(*ctx));
1841         if (!adev->fw_vram_usage.mem_train_support) {
1842                 DRM_DEBUG("memory training does not support!\n");
1843                 return 0;
1844         }
1845
1846         ctx->c2p_train_data_offset = amdgpu_ttm_training_get_c2p_offset(adev->gmc.mc_vram_size);
1847         ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1848         ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1849
1850         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1851                   ctx->train_data_size,
1852                   ctx->p2c_train_data_offset,
1853                   ctx->c2p_train_data_offset);
1854
1855         ret = amdgpu_bo_create_kernel_at(adev,
1856                                          ctx->c2p_train_data_offset,
1857                                          ctx->train_data_size,
1858                                          AMDGPU_GEM_DOMAIN_VRAM,
1859                                          &ctx->c2p_bo,
1860                                          NULL);
1861         if (ret) {
1862                 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1863                 amdgpu_ttm_training_reserve_vram_fini(adev);
1864                 return ret;
1865         }
1866
1867         ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1868         return 0;
1869 }
1870
1871 /**
1872  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1873  * gtt/vram related fields.
1874  *
1875  * This initializes all of the memory space pools that the TTM layer
1876  * will need such as the GTT space (system memory mapped to the device),
1877  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1878  * can be mapped per VMID.
1879  */
1880 int amdgpu_ttm_init(struct amdgpu_device *adev)
1881 {
1882         uint64_t gtt_size;
1883         int r;
1884         u64 vis_vram_limit;
1885         void *stolen_vga_buf;
1886
1887         mutex_init(&adev->mman.gtt_window_lock);
1888
1889         /* No others user of address space so set it to 0 */
1890         r = ttm_bo_device_init(&adev->mman.bdev,
1891                                &amdgpu_bo_driver,
1892                                adev->ddev->anon_inode->i_mapping,
1893                                adev->ddev->vma_offset_manager,
1894                                dma_addressing_limited(adev->dev));
1895         if (r) {
1896                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1897                 return r;
1898         }
1899         adev->mman.initialized = true;
1900
1901         /* We opt to avoid OOM on system pages allocations */
1902         adev->mman.bdev.no_retry = true;
1903
1904         /* Initialize VRAM pool with all of VRAM divided into pages */
1905         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1906                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1907         if (r) {
1908                 DRM_ERROR("Failed initializing VRAM heap.\n");
1909                 return r;
1910         }
1911
1912         /* Reduce size of CPU-visible VRAM if requested */
1913         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1914         if (amdgpu_vis_vram_limit > 0 &&
1915             vis_vram_limit <= adev->gmc.visible_vram_size)
1916                 adev->gmc.visible_vram_size = vis_vram_limit;
1917
1918         /* Change the size here instead of the init above so only lpfn is affected */
1919         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1920 #ifdef CONFIG_64BIT
1921         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1922                                                 adev->gmc.visible_vram_size);
1923 #endif
1924
1925         /*
1926          *The reserved vram for firmware must be pinned to the specified
1927          *place on the VRAM, so reserve it early.
1928          */
1929         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1930         if (r) {
1931                 return r;
1932         }
1933
1934         /*
1935          *The reserved vram for memory training must be pinned to the specified
1936          *place on the VRAM, so reserve it early.
1937          */
1938         if (!amdgpu_sriov_vf(adev)) {
1939                 r = amdgpu_ttm_training_reserve_vram_init(adev);
1940                 if (r)
1941                         return r;
1942         }
1943
1944         /* allocate memory as required for VGA
1945          * This is used for VGA emulation and pre-OS scanout buffers to
1946          * avoid display artifacts while transitioning between pre-OS
1947          * and driver.  */
1948         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1949                                     AMDGPU_GEM_DOMAIN_VRAM,
1950                                     &adev->stolen_vga_memory,
1951                                     NULL, &stolen_vga_buf);
1952         if (r)
1953                 return r;
1954
1955         /*
1956          * reserve TMR memory at the top of VRAM which holds
1957          * IP Discovery data and is protected by PSP.
1958          */
1959         if (adev->discovery_tmr_size > 0) {
1960                 r = amdgpu_bo_create_kernel_at(adev,
1961                         adev->gmc.real_vram_size - adev->discovery_tmr_size,
1962                         adev->discovery_tmr_size,
1963                         AMDGPU_GEM_DOMAIN_VRAM,
1964                         &adev->discovery_memory,
1965                         NULL);
1966                 if (r)
1967                         return r;
1968         }
1969
1970         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1971                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1972
1973         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1974          * or whatever the user passed on module init */
1975         if (amdgpu_gtt_size == -1) {
1976                 struct sysinfo si;
1977
1978                 si_meminfo(&si);
1979                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1980                                adev->gmc.mc_vram_size),
1981                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1982         }
1983         else
1984                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1985
1986         /* Initialize GTT memory pool */
1987         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1988         if (r) {
1989                 DRM_ERROR("Failed initializing GTT heap.\n");
1990                 return r;
1991         }
1992         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1993                  (unsigned)(gtt_size / (1024 * 1024)));
1994
1995         /* Initialize various on-chip memory pools */
1996         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1997                            adev->gds.gds_size);
1998         if (r) {
1999                 DRM_ERROR("Failed initializing GDS heap.\n");
2000                 return r;
2001         }
2002
2003         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
2004                            adev->gds.gws_size);
2005         if (r) {
2006                 DRM_ERROR("Failed initializing gws heap.\n");
2007                 return r;
2008         }
2009
2010         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
2011                            adev->gds.oa_size);
2012         if (r) {
2013                 DRM_ERROR("Failed initializing oa heap.\n");
2014                 return r;
2015         }
2016
2017         return 0;
2018 }
2019
2020 /**
2021  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2022  */
2023 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2024 {
2025         void *stolen_vga_buf;
2026         /* return the VGA stolen memory (if any) back to VRAM */
2027         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
2028 }
2029
2030 /**
2031  * amdgpu_ttm_fini - De-initialize the TTM memory pools
2032  */
2033 void amdgpu_ttm_fini(struct amdgpu_device *adev)
2034 {
2035         if (!adev->mman.initialized)
2036                 return;
2037
2038         amdgpu_ttm_training_reserve_vram_fini(adev);
2039         /* return the IP Discovery TMR memory back to VRAM */
2040         amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
2041         amdgpu_ttm_fw_reserve_vram_fini(adev);
2042
2043         if (adev->mman.aper_base_kaddr)
2044                 iounmap(adev->mman.aper_base_kaddr);
2045         adev->mman.aper_base_kaddr = NULL;
2046
2047         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
2048         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
2049         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
2050         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
2051         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
2052         ttm_bo_device_release(&adev->mman.bdev);
2053         adev->mman.initialized = false;
2054         DRM_INFO("amdgpu: ttm finalized\n");
2055 }
2056
2057 /**
2058  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2059  *
2060  * @adev: amdgpu_device pointer
2061  * @enable: true when we can use buffer functions.
2062  *
2063  * Enable/disable use of buffer functions during suspend/resume. This should
2064  * only be called at bootup or when userspace isn't running.
2065  */
2066 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2067 {
2068         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
2069         uint64_t size;
2070         int r;
2071
2072         if (!adev->mman.initialized || adev->in_gpu_reset ||
2073             adev->mman.buffer_funcs_enabled == enable)
2074                 return;
2075
2076         if (enable) {
2077                 struct amdgpu_ring *ring;
2078                 struct drm_gpu_scheduler *sched;
2079
2080                 ring = adev->mman.buffer_funcs_ring;
2081                 sched = &ring->sched;
2082                 r = drm_sched_entity_init(&adev->mman.entity,
2083                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
2084                                           1, NULL);
2085                 if (r) {
2086                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2087                                   r);
2088                         return;
2089                 }
2090         } else {
2091                 drm_sched_entity_destroy(&adev->mman.entity);
2092                 dma_fence_put(man->move);
2093                 man->move = NULL;
2094         }
2095
2096         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2097         if (enable)
2098                 size = adev->gmc.real_vram_size;
2099         else
2100                 size = adev->gmc.visible_vram_size;
2101         man->size = size >> PAGE_SHIFT;
2102         adev->mman.buffer_funcs_enabled = enable;
2103 }
2104
2105 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2106 {
2107         struct drm_file *file_priv = filp->private_data;
2108         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
2109
2110         if (adev == NULL)
2111                 return -EINVAL;
2112
2113         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2114 }
2115
2116 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2117                        uint64_t dst_offset, uint32_t byte_count,
2118                        struct dma_resv *resv,
2119                        struct dma_fence **fence, bool direct_submit,
2120                        bool vm_needs_flush, bool tmz)
2121 {
2122         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2123                 AMDGPU_IB_POOL_DELAYED;
2124         struct amdgpu_device *adev = ring->adev;
2125         struct amdgpu_job *job;
2126
2127         uint32_t max_bytes;
2128         unsigned num_loops, num_dw;
2129         unsigned i;
2130         int r;
2131
2132         if (direct_submit && !ring->sched.ready) {
2133                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2134                 return -EINVAL;
2135         }
2136
2137         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2138         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2139         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2140
2141         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2142         if (r)
2143                 return r;
2144
2145         if (vm_needs_flush) {
2146                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2147                 job->vm_needs_flush = true;
2148         }
2149         if (resv) {
2150                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2151                                      AMDGPU_SYNC_ALWAYS,
2152                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2153                 if (r) {
2154                         DRM_ERROR("sync failed (%d).\n", r);
2155                         goto error_free;
2156                 }
2157         }
2158
2159         for (i = 0; i < num_loops; i++) {
2160                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2161
2162                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2163                                         dst_offset, cur_size_in_bytes, tmz);
2164
2165                 src_offset += cur_size_in_bytes;
2166                 dst_offset += cur_size_in_bytes;
2167                 byte_count -= cur_size_in_bytes;
2168         }
2169
2170         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2171         WARN_ON(job->ibs[0].length_dw > num_dw);
2172         if (direct_submit)
2173                 r = amdgpu_job_submit_direct(job, ring, fence);
2174         else
2175                 r = amdgpu_job_submit(job, &adev->mman.entity,
2176                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2177         if (r)
2178                 goto error_free;
2179
2180         return r;
2181
2182 error_free:
2183         amdgpu_job_free(job);
2184         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2185         return r;
2186 }
2187
2188 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2189                        uint32_t src_data,
2190                        struct dma_resv *resv,
2191                        struct dma_fence **fence)
2192 {
2193         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2194         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2195         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2196
2197         struct drm_mm_node *mm_node;
2198         unsigned long num_pages;
2199         unsigned int num_loops, num_dw;
2200
2201         struct amdgpu_job *job;
2202         int r;
2203
2204         if (!adev->mman.buffer_funcs_enabled) {
2205                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2206                 return -EINVAL;
2207         }
2208
2209         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2210                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2211                 if (r)
2212                         return r;
2213         }
2214
2215         num_pages = bo->tbo.num_pages;
2216         mm_node = bo->tbo.mem.mm_node;
2217         num_loops = 0;
2218         while (num_pages) {
2219                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2220
2221                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2222                 num_pages -= mm_node->size;
2223                 ++mm_node;
2224         }
2225         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2226
2227         /* for IB padding */
2228         num_dw += 64;
2229
2230         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2231                                      &job);
2232         if (r)
2233                 return r;
2234
2235         if (resv) {
2236                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2237                                      AMDGPU_SYNC_ALWAYS,
2238                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2239                 if (r) {
2240                         DRM_ERROR("sync failed (%d).\n", r);
2241                         goto error_free;
2242                 }
2243         }
2244
2245         num_pages = bo->tbo.num_pages;
2246         mm_node = bo->tbo.mem.mm_node;
2247
2248         while (num_pages) {
2249                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2250                 uint64_t dst_addr;
2251
2252                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2253                 while (byte_count) {
2254                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2255                                                            max_bytes);
2256
2257                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2258                                                 dst_addr, cur_size_in_bytes);
2259
2260                         dst_addr += cur_size_in_bytes;
2261                         byte_count -= cur_size_in_bytes;
2262                 }
2263
2264                 num_pages -= mm_node->size;
2265                 ++mm_node;
2266         }
2267
2268         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2269         WARN_ON(job->ibs[0].length_dw > num_dw);
2270         r = amdgpu_job_submit(job, &adev->mman.entity,
2271                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2272         if (r)
2273                 goto error_free;
2274
2275         return 0;
2276
2277 error_free:
2278         amdgpu_job_free(job);
2279         return r;
2280 }
2281
2282 #if defined(CONFIG_DEBUG_FS)
2283
2284 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2285 {
2286         struct drm_info_node *node = (struct drm_info_node *)m->private;
2287         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2288         struct drm_device *dev = node->minor->dev;
2289         struct amdgpu_device *adev = dev->dev_private;
2290         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2291         struct drm_printer p = drm_seq_file_printer(m);
2292
2293         man->func->debug(man, &p);
2294         return 0;
2295 }
2296
2297 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2298         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2299         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2300         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2301         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2302         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2303         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2304 #ifdef CONFIG_SWIOTLB
2305         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2306 #endif
2307 };
2308
2309 /**
2310  * amdgpu_ttm_vram_read - Linear read access to VRAM
2311  *
2312  * Accesses VRAM via MMIO for debugging purposes.
2313  */
2314 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2315                                     size_t size, loff_t *pos)
2316 {
2317         struct amdgpu_device *adev = file_inode(f)->i_private;
2318         ssize_t result = 0;
2319
2320         if (size & 0x3 || *pos & 0x3)
2321                 return -EINVAL;
2322
2323         if (*pos >= adev->gmc.mc_vram_size)
2324                 return -ENXIO;
2325
2326         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2327         while (size) {
2328                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2329                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2330
2331                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2332                 if (copy_to_user(buf, value, bytes))
2333                         return -EFAULT;
2334
2335                 result += bytes;
2336                 buf += bytes;
2337                 *pos += bytes;
2338                 size -= bytes;
2339         }
2340
2341         return result;
2342 }
2343
2344 /**
2345  * amdgpu_ttm_vram_write - Linear write access to VRAM
2346  *
2347  * Accesses VRAM via MMIO for debugging purposes.
2348  */
2349 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2350                                     size_t size, loff_t *pos)
2351 {
2352         struct amdgpu_device *adev = file_inode(f)->i_private;
2353         ssize_t result = 0;
2354         int r;
2355
2356         if (size & 0x3 || *pos & 0x3)
2357                 return -EINVAL;
2358
2359         if (*pos >= adev->gmc.mc_vram_size)
2360                 return -ENXIO;
2361
2362         while (size) {
2363                 unsigned long flags;
2364                 uint32_t value;
2365
2366                 if (*pos >= adev->gmc.mc_vram_size)
2367                         return result;
2368
2369                 r = get_user(value, (uint32_t *)buf);
2370                 if (r)
2371                         return r;
2372
2373                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2374                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2375                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2376                 WREG32_NO_KIQ(mmMM_DATA, value);
2377                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2378
2379                 result += 4;
2380                 buf += 4;
2381                 *pos += 4;
2382                 size -= 4;
2383         }
2384
2385         return result;
2386 }
2387
2388 static const struct file_operations amdgpu_ttm_vram_fops = {
2389         .owner = THIS_MODULE,
2390         .read = amdgpu_ttm_vram_read,
2391         .write = amdgpu_ttm_vram_write,
2392         .llseek = default_llseek,
2393 };
2394
2395 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2396
2397 /**
2398  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2399  */
2400 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2401                                    size_t size, loff_t *pos)
2402 {
2403         struct amdgpu_device *adev = file_inode(f)->i_private;
2404         ssize_t result = 0;
2405         int r;
2406
2407         while (size) {
2408                 loff_t p = *pos / PAGE_SIZE;
2409                 unsigned off = *pos & ~PAGE_MASK;
2410                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2411                 struct page *page;
2412                 void *ptr;
2413
2414                 if (p >= adev->gart.num_cpu_pages)
2415                         return result;
2416
2417                 page = adev->gart.pages[p];
2418                 if (page) {
2419                         ptr = kmap(page);
2420                         ptr += off;
2421
2422                         r = copy_to_user(buf, ptr, cur_size);
2423                         kunmap(adev->gart.pages[p]);
2424                 } else
2425                         r = clear_user(buf, cur_size);
2426
2427                 if (r)
2428                         return -EFAULT;
2429
2430                 result += cur_size;
2431                 buf += cur_size;
2432                 *pos += cur_size;
2433                 size -= cur_size;
2434         }
2435
2436         return result;
2437 }
2438
2439 static const struct file_operations amdgpu_ttm_gtt_fops = {
2440         .owner = THIS_MODULE,
2441         .read = amdgpu_ttm_gtt_read,
2442         .llseek = default_llseek
2443 };
2444
2445 #endif
2446
2447 /**
2448  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2449  *
2450  * This function is used to read memory that has been mapped to the
2451  * GPU and the known addresses are not physical addresses but instead
2452  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2453  */
2454 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2455                                  size_t size, loff_t *pos)
2456 {
2457         struct amdgpu_device *adev = file_inode(f)->i_private;
2458         struct iommu_domain *dom;
2459         ssize_t result = 0;
2460         int r;
2461
2462         /* retrieve the IOMMU domain if any for this device */
2463         dom = iommu_get_domain_for_dev(adev->dev);
2464
2465         while (size) {
2466                 phys_addr_t addr = *pos & PAGE_MASK;
2467                 loff_t off = *pos & ~PAGE_MASK;
2468                 size_t bytes = PAGE_SIZE - off;
2469                 unsigned long pfn;
2470                 struct page *p;
2471                 void *ptr;
2472
2473                 bytes = bytes < size ? bytes : size;
2474
2475                 /* Translate the bus address to a physical address.  If
2476                  * the domain is NULL it means there is no IOMMU active
2477                  * and the address translation is the identity
2478                  */
2479                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2480
2481                 pfn = addr >> PAGE_SHIFT;
2482                 if (!pfn_valid(pfn))
2483                         return -EPERM;
2484
2485                 p = pfn_to_page(pfn);
2486                 if (p->mapping != adev->mman.bdev.dev_mapping)
2487                         return -EPERM;
2488
2489                 ptr = kmap(p);
2490                 r = copy_to_user(buf, ptr + off, bytes);
2491                 kunmap(p);
2492                 if (r)
2493                         return -EFAULT;
2494
2495                 size -= bytes;
2496                 *pos += bytes;
2497                 result += bytes;
2498         }
2499
2500         return result;
2501 }
2502
2503 /**
2504  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2505  *
2506  * This function is used to write memory that has been mapped to the
2507  * GPU and the known addresses are not physical addresses but instead
2508  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2509  */
2510 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2511                                  size_t size, loff_t *pos)
2512 {
2513         struct amdgpu_device *adev = file_inode(f)->i_private;
2514         struct iommu_domain *dom;
2515         ssize_t result = 0;
2516         int r;
2517
2518         dom = iommu_get_domain_for_dev(adev->dev);
2519
2520         while (size) {
2521                 phys_addr_t addr = *pos & PAGE_MASK;
2522                 loff_t off = *pos & ~PAGE_MASK;
2523                 size_t bytes = PAGE_SIZE - off;
2524                 unsigned long pfn;
2525                 struct page *p;
2526                 void *ptr;
2527
2528                 bytes = bytes < size ? bytes : size;
2529
2530                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2531
2532                 pfn = addr >> PAGE_SHIFT;
2533                 if (!pfn_valid(pfn))
2534                         return -EPERM;
2535
2536                 p = pfn_to_page(pfn);
2537                 if (p->mapping != adev->mman.bdev.dev_mapping)
2538                         return -EPERM;
2539
2540                 ptr = kmap(p);
2541                 r = copy_from_user(ptr + off, buf, bytes);
2542                 kunmap(p);
2543                 if (r)
2544                         return -EFAULT;
2545
2546                 size -= bytes;
2547                 *pos += bytes;
2548                 result += bytes;
2549         }
2550
2551         return result;
2552 }
2553
2554 static const struct file_operations amdgpu_ttm_iomem_fops = {
2555         .owner = THIS_MODULE,
2556         .read = amdgpu_iomem_read,
2557         .write = amdgpu_iomem_write,
2558         .llseek = default_llseek
2559 };
2560
2561 static const struct {
2562         char *name;
2563         const struct file_operations *fops;
2564         int domain;
2565 } ttm_debugfs_entries[] = {
2566         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2567 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2568         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2569 #endif
2570         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2571 };
2572
2573 #endif
2574
2575 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2576 {
2577 #if defined(CONFIG_DEBUG_FS)
2578         unsigned count;
2579
2580         struct drm_minor *minor = adev->ddev->primary;
2581         struct dentry *ent, *root = minor->debugfs_root;
2582
2583         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2584                 ent = debugfs_create_file(
2585                                 ttm_debugfs_entries[count].name,
2586                                 S_IFREG | S_IRUGO, root,
2587                                 adev,
2588                                 ttm_debugfs_entries[count].fops);
2589                 if (IS_ERR(ent))
2590                         return PTR_ERR(ent);
2591                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2592                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2593                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2594                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2595                 adev->mman.debugfs_entries[count] = ent;
2596         }
2597
2598         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2599
2600 #ifdef CONFIG_SWIOTLB
2601         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2602                 --count;
2603 #endif
2604
2605         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2606 #else
2607         return 0;
2608 #endif
2609 }