drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/sched/task.h>
  37 #include <linux/sched/mm.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/dma-buf.h>
  43 #include <linux/sizes.h>
  44
  45 #include <drm/ttm/ttm_bo_api.h>
  46 #include <drm/ttm/ttm_bo_driver.h>
  47 #include <drm/ttm/ttm_placement.h>
  48
  49 #include <drm/amdgpu_drm.h>
  50
  51 #include "amdgpu.h"
  52 #include "amdgpu_object.h"
  53 #include "amdgpu_trace.h"
  54 #include "amdgpu_amdkfd.h"
  55 #include "amdgpu_sdma.h"
  56 #include "amdgpu_ras.h"
  57 #include "amdgpu_atomfirmware.h"
  58 #include "amdgpu_res_cursor.h"
  59 #include "bif/bif_4_1_d.h"
  60
  61 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  62
  63 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  64                                    struct ttm_tt *ttm,
  65                                    struct ttm_resource *bo_mem);
  66 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  67                                       struct ttm_tt *ttm);
  68
  69 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  70                                     unsigned int type,
  71                                     uint64_t size_in_page)
  72 {
  73         return ttm_range_man_init(&adev->mman.bdev, type,
  74                                   false, size_in_page);
  75 }
  76
  77 /**
  78  * amdgpu_evict_flags - Compute placement flags
  79  *
  80  * @bo: The buffer object to evict
  81  * @placement: Possible destination(s) for evicted BO
  82  *
  83  * Fill in placement data when ttm_bo_evict() is called
  84  */
  85 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  86                                 struct ttm_placement *placement)
  87 {
  88         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  89         struct amdgpu_bo *abo;
  90         static const struct ttm_place placements = {
  91                 .fpfn = 0,
  92                 .lpfn = 0,
  93                 .mem_type = TTM_PL_SYSTEM,
  94                 .flags = 0
  95         };
  96
  97         /* Don't handle scatter gather BOs */
  98         if (bo->type == ttm_bo_type_sg) {
  99                 placement->num_placement = 0;
 100                 placement->num_busy_placement = 0;
 101                 return;
 102         }
 103
 104         /* Object isn't an AMDGPU object so ignore */
 105         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 106                 placement->placement = &placements;
 107                 placement->busy_placement = &placements;
 108                 placement->num_placement = 1;
 109                 placement->num_busy_placement = 1;
 110                 return;
 111         }
 112
 113         abo = ttm_to_amdgpu_bo(bo);
 114         if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) {
 115                 struct dma_fence *fence;
 116                 struct dma_resv *resv = &bo->base._resv;
 117
 118                 rcu_read_lock();
 119                 fence = rcu_dereference(resv->fence_excl);
 120                 if (fence && !fence->ops->signaled)
 121                         dma_fence_enable_sw_signaling(fence);
 122
 123                 placement->num_placement = 0;
 124                 placement->num_busy_placement = 0;
 125                 rcu_read_unlock();
 126                 return;
 127         }
 128         switch (bo->mem.mem_type) {
 129         case AMDGPU_PL_GDS:
 130         case AMDGPU_PL_GWS:
 131         case AMDGPU_PL_OA:
 132                 placement->num_placement = 0;
 133                 placement->num_busy_placement = 0;
 134                 return;
 135
 136         case TTM_PL_VRAM:
 137                 if (!adev->mman.buffer_funcs_enabled) {
 138                         /* Move to system memory */
 139                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 140                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 141                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 142                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 143
 144                         /* Try evicting to the CPU inaccessible part of VRAM
 145                          * first, but only set GTT as busy placement, so this
 146                          * BO will be evicted to GTT rather than causing other
 147                          * BOs to be evicted from VRAM
 148                          */
 149                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 150                                                          AMDGPU_GEM_DOMAIN_GTT);
 151                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 152                         abo->placements[0].lpfn = 0;
 153                         abo->placement.busy_placement = &abo->placements[1];
 154                         abo->placement.num_busy_placement = 1;
 155                 } else {
 156                         /* Move to GTT memory */
 157                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 158                 }
 159                 break;
 160         case TTM_PL_TT:
 161         default:
 162                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 163                 break;
 164         }
 165         *placement = abo->placement;
 166 }
 167
 168 /**
 169  * amdgpu_verify_access - Verify access for a mmap call
 170  *
 171  * @bo: The buffer object to map
 172  * @filp: The file pointer from the process performing the mmap
 173  *
 174  * This is called by ttm_bo_mmap() to verify whether a process
 175  * has the right to mmap a BO to their process space.
 176  */
 177 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 178 {
 179         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 180
 181         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 182                 return -EPERM;
 183         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 184                                           filp->private_data);
 185 }
 186
 187 /**
 188  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 189  * @bo: buffer object to map
 190  * @mem: memory object to map
 191  * @mm_cur: range to map
 192  * @num_pages: number of pages to map
 193  * @window: which GART window to use
 194  * @ring: DMA ring to use for the copy
 195  * @tmz: if we should setup a TMZ enabled mapping
 196  * @addr: resulting address inside the MC address space
 197  *
 198  * Setup one of the GART windows to access a specific piece of memory or return
 199  * the physical address for local memory.
 200  */
 201 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 202                                  struct ttm_resource *mem,
 203                                  struct amdgpu_res_cursor *mm_cur,
 204                                  unsigned num_pages, unsigned window,
 205                                  struct amdgpu_ring *ring, bool tmz,
 206                                  uint64_t *addr)
 207 {
 208         struct amdgpu_device *adev = ring->adev;
 209         struct amdgpu_job *job;
 210         unsigned num_dw, num_bytes;
 211         struct dma_fence *fence;
 212         uint64_t src_addr, dst_addr;
 213         void *cpu_addr;
 214         uint64_t flags;
 215         unsigned int i;
 216         int r;
 217
 218         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 219                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 220
 221         /* Map only what can't be accessed directly */
 222         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 223                 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 224                         mm_cur->start;
 225                 return 0;
 226         }
 227
 228         *addr = adev->gmc.gart_start;
 229         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 230                 AMDGPU_GPU_PAGE_SIZE;
 231         *addr += mm_cur->start & ~PAGE_MASK;
 232
 233         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 234         num_bytes = num_pages * 8;
 235
 236         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 237                                      AMDGPU_IB_POOL_DELAYED, &job);
 238         if (r)
 239                 return r;
 240
 241         src_addr = num_dw * 4;
 242         src_addr += job->ibs[0].gpu_addr;
 243
 244         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 245         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 246         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 247                                 dst_addr, num_bytes, false);
 248
 249         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 250         WARN_ON(job->ibs[0].length_dw > num_dw);
 251
 252         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 253         if (tmz)
 254                 flags |= AMDGPU_PTE_TMZ;
 255
 256         cpu_addr = &job->ibs[0].ptr[num_dw];
 257
 258         if (mem->mem_type == TTM_PL_TT) {
 259                 dma_addr_t *dma_addr;
 260
 261                 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 262                 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,
 263                                     cpu_addr);
 264                 if (r)
 265                         goto error_free;
 266         } else {
 267                 dma_addr_t dma_address;
 268
 269                 dma_address = mm_cur->start;
 270                 dma_address += adev->vm_manager.vram_base_offset;
 271
 272                 for (i = 0; i < num_pages; ++i) {
 273                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 274                                             &dma_address, flags, cpu_addr);
 275                         if (r)
 276                                 goto error_free;
 277
 278                         dma_address += PAGE_SIZE;
 279                 }
 280         }
 281
 282         r = amdgpu_job_submit(job, &adev->mman.entity,
 283                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 284         if (r)
 285                 goto error_free;
 286
 287         dma_fence_put(fence);
 288
 289         return r;
 290
 291 error_free:
 292         amdgpu_job_free(job);
 293         return r;
 294 }
 295
 296 /**
 297  * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
 298  * @adev: amdgpu device
 299  * @src: buffer/address where to read from
 300  * @dst: buffer/address where to write to
 301  * @size: number of bytes to copy
 302  * @tmz: if a secure copy should be used
 303  * @resv: resv object to sync to
 304  * @f: Returns the last fence if multiple jobs are submitted.
 305  *
 306  * The function copies @size bytes from {src->mem + src->offset} to
 307  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 308  * move and different for a BO to BO copy.
 309  *
 310  */
 311 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 312                                const struct amdgpu_copy_mem *src,
 313                                const struct amdgpu_copy_mem *dst,
 314                                uint64_t size, bool tmz,
 315                                struct dma_resv *resv,
 316                                struct dma_fence **f)
 317 {
 318         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 319                                         AMDGPU_GPU_PAGE_SIZE);
 320
 321         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 322         struct amdgpu_res_cursor src_mm, dst_mm;
 323         struct dma_fence *fence = NULL;
 324         int r = 0;
 325
 326         if (!adev->mman.buffer_funcs_enabled) {
 327                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 328                 return -EINVAL;
 329         }
 330
 331         amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 332         amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 333
 334         mutex_lock(&adev->mman.gtt_window_lock);
 335         while (src_mm.remaining) {
 336                 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;
 337                 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;
 338                 struct dma_fence *next;
 339                 uint32_t cur_size;
 340                 uint64_t from, to;
 341
 342                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 343                  * begins at an offset, then adjust the size accordingly
 344                  */
 345                 cur_size = max(src_page_offset, dst_page_offset);
 346                 cur_size = min(min3(src_mm.size, dst_mm.size, size),
 347                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 348
 349                 /* Map src to window 0 and dst to window 1. */
 350                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 351                                           PFN_UP(cur_size + src_page_offset),
 352                                           0, ring, tmz, &from);
 353                 if (r)
 354                         goto error;
 355
 356                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 357                                           PFN_UP(cur_size + dst_page_offset),
 358                                           1, ring, tmz, &to);
 359                 if (r)
 360                         goto error;
 361
 362                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 363                                        resv, &next, false, true, tmz);
 364                 if (r)
 365                         goto error;
 366
 367                 dma_fence_put(fence);
 368                 fence = next;
 369
 370                 amdgpu_res_next(&src_mm, cur_size);
 371                 amdgpu_res_next(&dst_mm, cur_size);
 372         }
 373 error:
 374         mutex_unlock(&adev->mman.gtt_window_lock);
 375         if (f)
 376                 *f = dma_fence_get(fence);
 377         dma_fence_put(fence);
 378         return r;
 379 }
 380
 381 /*
 382  * amdgpu_move_blit - Copy an entire buffer to another buffer
 383  *
 384  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 385  * help move buffers to and from VRAM.
 386  */
 387 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 388                             bool evict,
 389                             struct ttm_resource *new_mem,
 390                             struct ttm_resource *old_mem)
 391 {
 392         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 393         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 394         struct amdgpu_copy_mem src, dst;
 395         struct dma_fence *fence = NULL;
 396         int r;
 397
 398         src.bo = bo;
 399         dst.bo = bo;
 400         src.mem = old_mem;
 401         dst.mem = new_mem;
 402         src.offset = 0;
 403         dst.offset = 0;
 404
 405         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 406                                        new_mem->num_pages << PAGE_SHIFT,
 407                                        amdgpu_bo_encrypted(abo),
 408                                        bo->base.resv, &fence);
 409         if (r)
 410                 goto error;
 411
 412         /* clear the space being freed */
 413         if (old_mem->mem_type == TTM_PL_VRAM &&
 414             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 415                 struct dma_fence *wipe_fence = NULL;
 416
 417                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 418                                        NULL, &wipe_fence);
 419                 if (r) {
 420                         goto error;
 421                 } else if (wipe_fence) {
 422                         dma_fence_put(fence);
 423                         fence = wipe_fence;
 424                 }
 425         }
 426
 427         /* Always block for VM page tables before committing the new location */
 428         if (bo->type == ttm_bo_type_kernel)
 429                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 430         else
 431                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 432         dma_fence_put(fence);
 433         return r;
 434
 435 error:
 436         if (fence)
 437                 dma_fence_wait(fence, false);
 438         dma_fence_put(fence);
 439         return r;
 440 }
 441
 442 /*
 443  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 444  *
 445  * Called by amdgpu_bo_move()
 446  */
 447 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 448                                struct ttm_resource *mem)
 449 {
 450         uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT;
 451         struct amdgpu_res_cursor cursor;
 452
 453         if (mem->mem_type == TTM_PL_SYSTEM ||
 454             mem->mem_type == TTM_PL_TT)
 455                 return true;
 456         if (mem->mem_type != TTM_PL_VRAM)
 457                 return false;
 458
 459         amdgpu_res_first(mem, 0, mem_size, &cursor);
 460
 461         /* ttm_resource_ioremap only supports contiguous memory */
 462         if (cursor.size != mem_size)
 463                 return false;
 464
 465         return cursor.start + cursor.size <= adev->gmc.visible_vram_size;
 466 }
 467
 468 /*
 469  * amdgpu_bo_move - Move a buffer object to a new memory location
 470  *
 471  * Called by ttm_bo_handle_move_mem()
 472  */
 473 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 474                           struct ttm_operation_ctx *ctx,
 475                           struct ttm_resource *new_mem,
 476                           struct ttm_place *hop)
 477 {
 478         struct amdgpu_device *adev;
 479         struct amdgpu_bo *abo;
 480         struct ttm_resource *old_mem = &bo->mem;
 481         int r;
 482
 483         if (new_mem->mem_type == TTM_PL_TT) {
 484                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 485                 if (r)
 486                         return r;
 487         }
 488
 489         /* Can't move a pinned BO */
 490         abo = ttm_to_amdgpu_bo(bo);
 491         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 492                 return -EINVAL;
 493
 494         adev = amdgpu_ttm_adev(bo->bdev);
 495
 496         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 497                 ttm_bo_move_null(bo, new_mem);
 498                 goto out;
 499         }
 500         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 501             new_mem->mem_type == TTM_PL_TT) {
 502                 ttm_bo_move_null(bo, new_mem);
 503                 goto out;
 504         }
 505         if (old_mem->mem_type == TTM_PL_TT &&
 506             new_mem->mem_type == TTM_PL_SYSTEM) {
 507                 r = ttm_bo_wait_ctx(bo, ctx);
 508                 if (r)
 509                         return r;
 510
 511                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 512                 ttm_resource_free(bo, &bo->mem);
 513                 ttm_bo_assign_mem(bo, new_mem);
 514                 goto out;
 515         }
 516
 517         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 518             old_mem->mem_type == AMDGPU_PL_GWS ||
 519             old_mem->mem_type == AMDGPU_PL_OA ||
 520             new_mem->mem_type == AMDGPU_PL_GDS ||
 521             new_mem->mem_type == AMDGPU_PL_GWS ||
 522             new_mem->mem_type == AMDGPU_PL_OA) {
 523                 /* Nothing to save here */
 524                 ttm_bo_move_null(bo, new_mem);
 525                 goto out;
 526         }
 527
 528         if (adev->mman.buffer_funcs_enabled) {
 529                 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 530                       new_mem->mem_type == TTM_PL_VRAM) ||
 531                      (old_mem->mem_type == TTM_PL_VRAM &&
 532                       new_mem->mem_type == TTM_PL_SYSTEM))) {
 533                         hop->fpfn = 0;
 534                         hop->lpfn = 0;
 535                         hop->mem_type = TTM_PL_TT;
 536                         hop->flags = 0;
 537                         return -EMULTIHOP;
 538                 }
 539
 540                 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 541         } else {
 542                 r = -ENODEV;
 543         }
 544
 545         if (r) {
 546                 /* Check that all memory is CPU accessible */
 547                 if (!amdgpu_mem_visible(adev, old_mem) ||
 548                     !amdgpu_mem_visible(adev, new_mem)) {
 549                         pr_err("Move buffer fallback to memcpy unavailable\n");
 550                         return r;
 551                 }
 552
 553                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 554                 if (r)
 555                         return r;
 556         }
 557
 558         if (bo->type == ttm_bo_type_device &&
 559             new_mem->mem_type == TTM_PL_VRAM &&
 560             old_mem->mem_type != TTM_PL_VRAM) {
 561                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 562                  * accesses the BO after it's moved.
 563                  */
 564                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 565         }
 566
 567 out:
 568         /* update statistics */
 569         atomic64_add(bo->base.size, &adev->num_bytes_moved);
 570         amdgpu_bo_move_notify(bo, evict, new_mem);
 571         return 0;
 572 }
 573
 574 /*
 575  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 576  *
 577  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 578  */
 579 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem)
 580 {
 581         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 582         struct drm_mm_node *mm_node = mem->mm_node;
 583         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 584
 585         switch (mem->mem_type) {
 586         case TTM_PL_SYSTEM:
 587                 /* system memory */
 588                 return 0;
 589         case TTM_PL_TT:
 590                 break;
 591         case TTM_PL_VRAM:
 592                 mem->bus.offset = mem->start << PAGE_SHIFT;
 593                 /* check if it's visible */
 594                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 595                         return -EINVAL;
 596                 /* Only physically contiguous buffers apply. In a contiguous
 597                  * buffer, size of the first mm_node would match the number of
 598                  * pages in ttm_resource.
 599                  */
 600                 if (adev->mman.aper_base_kaddr &&
 601                     (mm_node->size == mem->num_pages))
 602                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 603                                         mem->bus.offset;
 604
 605                 mem->bus.offset += adev->gmc.aper_base;
 606                 mem->bus.is_iomem = true;
 607                 if (adev->gmc.xgmi.connected_to_cpu)
 608                         mem->bus.caching = ttm_cached;
 609                 else
 610                         mem->bus.caching = ttm_write_combined;
 611                 break;
 612         default:
 613                 return -EINVAL;
 614         }
 615         return 0;
 616 }
 617
 618 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 619                                            unsigned long page_offset)
 620 {
 621         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 622         struct amdgpu_res_cursor cursor;
 623
 624         amdgpu_res_first(&bo->mem, (u64)page_offset << PAGE_SHIFT, 0, &cursor);
 625         return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 626 }
 627
 628 /**
 629  * amdgpu_ttm_domain_start - Returns GPU start address
 630  * @adev: amdgpu device object
 631  * @type: type of the memory
 632  *
 633  * Returns:
 634  * GPU start address of a memory domain
 635  */
 636
 637 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 638 {
 639         switch (type) {
 640         case TTM_PL_TT:
 641                 return adev->gmc.gart_start;
 642         case TTM_PL_VRAM:
 643                 return adev->gmc.vram_start;
 644         }
 645
 646         return 0;
 647 }
 648
 649 /*
 650  * TTM backend functions.
 651  */
 652 struct amdgpu_ttm_tt {
 653         struct ttm_tt   ttm;
 654         struct drm_gem_object   *gobj;
 655         u64                     offset;
 656         uint64_t                userptr;
 657         struct task_struct      *usertask;
 658         uint32_t                userflags;
 659         bool                    bound;
 660 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 661         struct hmm_range        *range;
 662 #endif
 663 };
 664
 665 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 666 /*
 667  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 668  * memory and start HMM tracking CPU page table update
 669  *
 670  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 671  * once afterwards to stop HMM tracking
 672  */
 673 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 674 {
 675         struct ttm_tt *ttm = bo->tbo.ttm;
 676         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 677         unsigned long start = gtt->userptr;
 678         struct vm_area_struct *vma;
 679         struct mm_struct *mm;
 680         bool readonly;
 681         int r = 0;
 682
 683         mm = bo->notifier.mm;
 684         if (unlikely(!mm)) {
 685                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 686                 return -EFAULT;
 687         }
 688
 689         /* Another get_user_pages is running at the same time?? */
 690         if (WARN_ON(gtt->range))
 691                 return -EFAULT;
 692
 693         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 694                 return -ESRCH;
 695
 696         mmap_read_lock(mm);
 697         vma = find_vma(mm, start);
 698         mmap_read_unlock(mm);
 699         if (unlikely(!vma || start < vma->vm_start)) {
 700                 r = -EFAULT;
 701                 goto out_putmm;
 702         }
 703         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 704                 vma->vm_file)) {
 705                 r = -EPERM;
 706                 goto out_putmm;
 707         }
 708
 709         readonly = amdgpu_ttm_tt_is_readonly(ttm);
 710         r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start,
 711                                        ttm->num_pages, &gtt->range, readonly,
 712                                        false);
 713 out_putmm:
 714         mmput(mm);
 715
 716         return r;
 717 }
 718
 719 /*
 720  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 721  * Check if the pages backing this ttm range have been invalidated
 722  *
 723  * Returns: true if pages are still valid
 724  */
 725 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 726 {
 727         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 728         bool r = false;
 729
 730         if (!gtt || !gtt->userptr)
 731                 return false;
 732
 733         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 734                 gtt->userptr, ttm->num_pages);
 735
 736         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 737                 "No user pages to check\n");
 738
 739         if (gtt->range) {
 740                 /*
 741                  * FIXME: Must always hold notifier_lock for this, and must
 742                  * not ignore the return code.
 743                  */
 744                 r = amdgpu_hmm_range_get_pages_done(gtt->range);
 745                 gtt->range = NULL;
 746         }
 747
 748         return !r;
 749 }
 750 #endif
 751
 752 /*
 753  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 754  *
 755  * Called by amdgpu_cs_list_validate(). This creates the page list
 756  * that backs user memory and will ultimately be mapped into the device
 757  * address space.
 758  */
 759 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 760 {
 761         unsigned long i;
 762
 763         for (i = 0; i < ttm->num_pages; ++i)
 764                 ttm->pages[i] = pages ? pages[i] : NULL;
 765 }
 766
 767 /*
 768  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 769  *
 770  * Called by amdgpu_ttm_backend_bind()
 771  **/
 772 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 773                                      struct ttm_tt *ttm)
 774 {
 775         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 776         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 777         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 778         enum dma_data_direction direction = write ?
 779                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 780         int r;
 781
 782         /* Allocate an SG array and squash pages into it */
 783         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 784                                       (u64)ttm->num_pages << PAGE_SHIFT,
 785                                       GFP_KERNEL);
 786         if (r)
 787                 goto release_sg;
 788
 789         /* Map SG to device */
 790         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 791         if (r)
 792                 goto release_sg;
 793
 794         /* convert SG to linear array of pages and dma addresses */
 795         drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 796                                        ttm->num_pages);
 797
 798         return 0;
 799
 800 release_sg:
 801         kfree(ttm->sg);
 802         ttm->sg = NULL;
 803         return r;
 804 }
 805
 806 /*
 807  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 808  */
 809 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 810                                         struct ttm_tt *ttm)
 811 {
 812         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 813         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 814         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 815         enum dma_data_direction direction = write ?
 816                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 817
 818         /* double check that we don't free the table twice */
 819         if (!ttm->sg || !ttm->sg->sgl)
 820                 return;
 821
 822         /* unmap the pages mapped to the device */
 823         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 824         sg_free_table(ttm->sg);
 825
 826 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 827         if (gtt->range) {
 828                 unsigned long i;
 829
 830                 for (i = 0; i < ttm->num_pages; i++) {
 831                         if (ttm->pages[i] !=
 832                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
 833                                 break;
 834                 }
 835
 836                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
 837         }
 838 #endif
 839 }
 840
 841 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 842                                 struct ttm_buffer_object *tbo,
 843                                 uint64_t flags)
 844 {
 845         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 846         struct ttm_tt *ttm = tbo->ttm;
 847         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 848         int r;
 849
 850         if (amdgpu_bo_encrypted(abo))
 851                 flags |= AMDGPU_PTE_TMZ;
 852
 853         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 854                 uint64_t page_idx = 1;
 855
 856                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 857                                 ttm->pages, gtt->ttm.dma_address, flags);
 858                 if (r)
 859                         goto gart_bind_fail;
 860
 861                 /* The memory type of the first page defaults to UC. Now
 862                  * modify the memory type to NC from the second page of
 863                  * the BO onward.
 864                  */
 865                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 866                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 867
 868                 r = amdgpu_gart_bind(adev,
 869                                 gtt->offset + (page_idx << PAGE_SHIFT),
 870                                 ttm->num_pages - page_idx,
 871                                 &ttm->pages[page_idx],
 872                                 &(gtt->ttm.dma_address[page_idx]), flags);
 873         } else {
 874                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 875                                      ttm->pages, gtt->ttm.dma_address, flags);
 876         }
 877
 878 gart_bind_fail:
 879         if (r)
 880                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 881                           ttm->num_pages, gtt->offset);
 882
 883         return r;
 884 }
 885
 886 /*
 887  * amdgpu_ttm_backend_bind - Bind GTT memory
 888  *
 889  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 890  * This handles binding GTT memory to the device address space.
 891  */
 892 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 893                                    struct ttm_tt *ttm,
 894                                    struct ttm_resource *bo_mem)
 895 {
 896         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 897         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 898         uint64_t flags;
 899         int r = 0;
 900
 901         if (!bo_mem)
 902                 return -EINVAL;
 903
 904         if (gtt->bound)
 905                 return 0;
 906
 907         if (gtt->userptr) {
 908                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 909                 if (r) {
 910                         DRM_ERROR("failed to pin userptr\n");
 911                         return r;
 912                 }
 913         }
 914         if (!ttm->num_pages) {
 915                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 916                      ttm->num_pages, bo_mem, ttm);
 917         }
 918
 919         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 920             bo_mem->mem_type == AMDGPU_PL_GWS ||
 921             bo_mem->mem_type == AMDGPU_PL_OA)
 922                 return -EINVAL;
 923
 924         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 925                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 926                 return 0;
 927         }
 928
 929         /* compute PTE flags relevant to this BO memory */
 930         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 931
 932         /* bind pages into GART page tables */
 933         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 934         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 935                 ttm->pages, gtt->ttm.dma_address, flags);
 936
 937         if (r)
 938                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 939                           ttm->num_pages, gtt->offset);
 940         gtt->bound = true;
 941         return r;
 942 }
 943
 944 /*
 945  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 946  * through AGP or GART aperture.
 947  *
 948  * If bo is accessible through AGP aperture, then use AGP aperture
 949  * to access bo; otherwise allocate logical space in GART aperture
 950  * and map bo to GART aperture.
 951  */
 952 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 953 {
 954         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 955         struct ttm_operation_ctx ctx = { false, false };
 956         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
 957         struct ttm_resource tmp;
 958         struct ttm_placement placement;
 959         struct ttm_place placements;
 960         uint64_t addr, flags;
 961         int r;
 962
 963         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
 964                 return 0;
 965
 966         addr = amdgpu_gmc_agp_addr(bo);
 967         if (addr != AMDGPU_BO_INVALID_OFFSET) {
 968                 bo->mem.start = addr >> PAGE_SHIFT;
 969         } else {
 970
 971                 /* allocate GART space */
 972                 placement.num_placement = 1;
 973                 placement.placement = &placements;
 974                 placement.num_busy_placement = 1;
 975                 placement.busy_placement = &placements;
 976                 placements.fpfn = 0;
 977                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 978                 placements.mem_type = TTM_PL_TT;
 979                 placements.flags = bo->mem.placement;
 980
 981                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 982                 if (unlikely(r))
 983                         return r;
 984
 985                 /* compute PTE flags for this buffer object */
 986                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
 987
 988                 /* Bind pages */
 989                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
 990                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
 991                 if (unlikely(r)) {
 992                         ttm_resource_free(bo, &tmp);
 993                         return r;
 994                 }
 995
 996                 ttm_resource_free(bo, &bo->mem);
 997                 bo->mem = tmp;
 998         }
 999
1000         return 0;
1001 }
1002
1003 /*
1004  * amdgpu_ttm_recover_gart - Rebind GTT pages
1005  *
1006  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1007  * rebind GTT pages during a GPU reset.
1008  */
1009 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1010 {
1011         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1012         uint64_t flags;
1013         int r;
1014
1015         if (!tbo->ttm)
1016                 return 0;
1017
1018         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1019         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1020
1021         return r;
1022 }
1023
1024 /*
1025  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1026  *
1027  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1028  * ttm_tt_destroy().
1029  */
1030 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1031                                       struct ttm_tt *ttm)
1032 {
1033         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1034         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1035         int r;
1036
1037         /* if the pages have userptr pinning then clear that first */
1038         if (gtt->userptr)
1039                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1040
1041         if (!gtt->bound)
1042                 return;
1043
1044         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1045                 return;
1046
1047         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1048         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1049         if (r)
1050                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1051                           gtt->ttm.num_pages, gtt->offset);
1052         gtt->bound = false;
1053 }
1054
1055 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1056                                        struct ttm_tt *ttm)
1057 {
1058         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1059
1060         amdgpu_ttm_backend_unbind(bdev, ttm);
1061         ttm_tt_destroy_common(bdev, ttm);
1062         if (gtt->usertask)
1063                 put_task_struct(gtt->usertask);
1064
1065         ttm_tt_fini(&gtt->ttm);
1066         kfree(gtt);
1067 }
1068
1069 /**
1070  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1071  *
1072  * @bo: The buffer object to create a GTT ttm_tt object around
1073  * @page_flags: Page flags to be added to the ttm_tt object
1074  *
1075  * Called by ttm_tt_create().
1076  */
1077 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1078                                            uint32_t page_flags)
1079 {
1080         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1081         struct amdgpu_ttm_tt *gtt;
1082         enum ttm_caching caching;
1083
1084         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1085         if (gtt == NULL) {
1086                 return NULL;
1087         }
1088         gtt->gobj = &bo->base;
1089
1090         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1091                 caching = ttm_write_combined;
1092         else
1093                 caching = ttm_cached;
1094
1095         /* allocate space for the uninitialized page entries */
1096         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1097                 kfree(gtt);
1098                 return NULL;
1099         }
1100         return &gtt->ttm;
1101 }
1102
1103 /*
1104  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1105  *
1106  * Map the pages of a ttm_tt object to an address space visible
1107  * to the underlying device.
1108  */
1109 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1110                                   struct ttm_tt *ttm,
1111                                   struct ttm_operation_ctx *ctx)
1112 {
1113         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1114         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1115
1116         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1117         if (gtt && gtt->userptr) {
1118                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1119                 if (!ttm->sg)
1120                         return -ENOMEM;
1121
1122                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1123                 return 0;
1124         }
1125
1126         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1127                 if (!ttm->sg) {
1128                         struct dma_buf_attachment *attach;
1129                         struct sg_table *sgt;
1130
1131                         attach = gtt->gobj->import_attach;
1132                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1133                         if (IS_ERR(sgt))
1134                                 return PTR_ERR(sgt);
1135
1136                         ttm->sg = sgt;
1137                 }
1138
1139                 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
1140                                                ttm->num_pages);
1141                 return 0;
1142         }
1143
1144         return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1145 }
1146
1147 /*
1148  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1149  *
1150  * Unmaps pages of a ttm_tt object from the device address space and
1151  * unpopulates the page array backing it.
1152  */
1153 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1154                                      struct ttm_tt *ttm)
1155 {
1156         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1157         struct amdgpu_device *adev;
1158
1159         if (gtt && gtt->userptr) {
1160                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1161                 kfree(ttm->sg);
1162                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1163                 return;
1164         }
1165
1166         if (ttm->sg && gtt->gobj->import_attach) {
1167                 struct dma_buf_attachment *attach;
1168
1169                 attach = gtt->gobj->import_attach;
1170                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1171                 ttm->sg = NULL;
1172                 return;
1173         }
1174
1175         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1176                 return;
1177
1178         adev = amdgpu_ttm_adev(bdev);
1179         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1180 }
1181
1182 /**
1183  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1184  * task
1185  *
1186  * @bo: The ttm_buffer_object to bind this userptr to
1187  * @addr:  The address in the current tasks VM space to use
1188  * @flags: Requirements of userptr object.
1189  *
1190  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1191  * to current task
1192  */
1193 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1194                               uint64_t addr, uint32_t flags)
1195 {
1196         struct amdgpu_ttm_tt *gtt;
1197
1198         if (!bo->ttm) {
1199                 /* TODO: We want a separate TTM object type for userptrs */
1200                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1201                 if (bo->ttm == NULL)
1202                         return -ENOMEM;
1203         }
1204
1205         gtt = (void *)bo->ttm;
1206         gtt->userptr = addr;
1207         gtt->userflags = flags;
1208
1209         if (gtt->usertask)
1210                 put_task_struct(gtt->usertask);
1211         gtt->usertask = current->group_leader;
1212         get_task_struct(gtt->usertask);
1213
1214         return 0;
1215 }
1216
1217 /*
1218  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1219  */
1220 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1221 {
1222         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1223
1224         if (gtt == NULL)
1225                 return NULL;
1226
1227         if (gtt->usertask == NULL)
1228                 return NULL;
1229
1230         return gtt->usertask->mm;
1231 }
1232
1233 /*
1234  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1235  * address range for the current task.
1236  *
1237  */
1238 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1239                                   unsigned long end)
1240 {
1241         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1242         unsigned long size;
1243
1244         if (gtt == NULL || !gtt->userptr)
1245                 return false;
1246
1247         /* Return false if no part of the ttm_tt object lies within
1248          * the range
1249          */
1250         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1251         if (gtt->userptr > end || gtt->userptr + size <= start)
1252                 return false;
1253
1254         return true;
1255 }
1256
1257 /*
1258  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1259  */
1260 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1261 {
1262         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1263
1264         if (gtt == NULL || !gtt->userptr)
1265                 return false;
1266
1267         return true;
1268 }
1269
1270 /*
1271  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1272  */
1273 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1274 {
1275         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1276
1277         if (gtt == NULL)
1278                 return false;
1279
1280         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1281 }
1282
1283 /**
1284  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1285  *
1286  * @ttm: The ttm_tt object to compute the flags for
1287  * @mem: The memory registry backing this ttm_tt object
1288  *
1289  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1290  */
1291 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1292 {
1293         uint64_t flags = 0;
1294
1295         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1296                 flags |= AMDGPU_PTE_VALID;
1297
1298         if (mem && mem->mem_type == TTM_PL_TT) {
1299                 flags |= AMDGPU_PTE_SYSTEM;
1300
1301                 if (ttm->caching == ttm_cached)
1302                         flags |= AMDGPU_PTE_SNOOPED;
1303         }
1304
1305         if (mem && mem->mem_type == TTM_PL_VRAM &&
1306                         mem->bus.caching == ttm_cached)
1307                 flags |= AMDGPU_PTE_SNOOPED;
1308
1309         return flags;
1310 }
1311
1312 /**
1313  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1314  *
1315  * @adev: amdgpu_device pointer
1316  * @ttm: The ttm_tt object to compute the flags for
1317  * @mem: The memory registry backing this ttm_tt object
1318  *
1319  * Figure out the flags to use for a VM PTE (Page Table Entry).
1320  */
1321 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1322                                  struct ttm_resource *mem)
1323 {
1324         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1325
1326         flags |= adev->gart.gart_pte_flags;
1327         flags |= AMDGPU_PTE_READABLE;
1328
1329         if (!amdgpu_ttm_tt_is_readonly(ttm))
1330                 flags |= AMDGPU_PTE_WRITEABLE;
1331
1332         return flags;
1333 }
1334
1335 /*
1336  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1337  * object.
1338  *
1339  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1340  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1341  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1342  * used to clean out a memory space.
1343  */
1344 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1345                                             const struct ttm_place *place)
1346 {
1347         unsigned long num_pages = bo->mem.num_pages;
1348         struct amdgpu_res_cursor cursor;
1349         struct dma_resv_list *flist;
1350         struct dma_fence *f;
1351         int i;
1352
1353         if (bo->type == ttm_bo_type_kernel &&
1354             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1355                 return false;
1356
1357         /* If bo is a KFD BO, check if the bo belongs to the current process.
1358          * If true, then return false as any KFD process needs all its BOs to
1359          * be resident to run successfully
1360          */
1361         flist = dma_resv_get_list(bo->base.resv);
1362         if (flist) {
1363                 for (i = 0; i < flist->shared_count; ++i) {
1364                         f = rcu_dereference_protected(flist->shared[i],
1365                                 dma_resv_held(bo->base.resv));
1366                         if (amdkfd_fence_check_mm(f, current->mm))
1367                                 return false;
1368                 }
1369         }
1370
1371         switch (bo->mem.mem_type) {
1372         case TTM_PL_TT:
1373                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1374                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1375                         return false;
1376                 return true;
1377
1378         case TTM_PL_VRAM:
1379                 /* Check each drm MM node individually */
1380                 amdgpu_res_first(&bo->mem, 0, (u64)num_pages << PAGE_SHIFT,
1381                                  &cursor);
1382                 while (cursor.remaining) {
1383                         if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
1384                             && !(place->lpfn &&
1385                                  place->lpfn <= PFN_DOWN(cursor.start)))
1386                                 return true;
1387
1388                         amdgpu_res_next(&cursor, cursor.size);
1389                 }
1390                 return false;
1391
1392         default:
1393                 break;
1394         }
1395
1396         return ttm_bo_eviction_valuable(bo, place);
1397 }
1398
1399 /**
1400  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1401  *
1402  * @bo:  The buffer object to read/write
1403  * @offset:  Offset into buffer object
1404  * @buf:  Secondary buffer to write/read from
1405  * @len: Length in bytes of access
1406  * @write:  true if writing
1407  *
1408  * This is used to access VRAM that backs a buffer object via MMIO
1409  * access for debugging purposes.
1410  */
1411 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1412                                     unsigned long offset, void *buf, int len,
1413                                     int write)
1414 {
1415         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1416         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1417         struct amdgpu_res_cursor cursor;
1418         unsigned long flags;
1419         uint32_t value = 0;
1420         int ret = 0;
1421
1422         if (bo->mem.mem_type != TTM_PL_VRAM)
1423                 return -EIO;
1424
1425         amdgpu_res_first(&bo->mem, offset, len, &cursor);
1426         while (cursor.remaining) {
1427                 uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
1428                 uint64_t bytes = 4 - (cursor.start & 3);
1429                 uint32_t shift = (cursor.start & 3) * 8;
1430                 uint32_t mask = 0xffffffff << shift;
1431
1432                 if (cursor.size < bytes) {
1433                         mask &= 0xffffffff >> (bytes - cursor.size) * 8;
1434                         bytes = cursor.size;
1435                 }
1436
1437                 if (mask != 0xffffffff) {
1438                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1439                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1440                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1441                         value = RREG32_NO_KIQ(mmMM_DATA);
1442                         if (write) {
1443                                 value &= ~mask;
1444                                 value |= (*(uint32_t *)buf << shift) & mask;
1445                                 WREG32_NO_KIQ(mmMM_DATA, value);
1446                         }
1447                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1448                         if (!write) {
1449                                 value = (value & mask) >> shift;
1450                                 memcpy(buf, &value, bytes);
1451                         }
1452                 } else {
1453                         bytes = cursor.size & ~0x3ULL;
1454                         amdgpu_device_vram_access(adev, cursor.start,
1455                                                   (uint32_t *)buf, bytes,
1456                                                   write);
1457                 }
1458
1459                 ret += bytes;
1460                 buf = (uint8_t *)buf + bytes;
1461                 amdgpu_res_next(&cursor, bytes);
1462         }
1463
1464         return ret;
1465 }
1466
1467 static void
1468 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1469 {
1470         amdgpu_bo_move_notify(bo, false, NULL);
1471 }
1472
1473 static struct ttm_device_funcs amdgpu_bo_driver = {
1474         .ttm_tt_create = &amdgpu_ttm_tt_create,
1475         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1476         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1477         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1478         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1479         .evict_flags = &amdgpu_evict_flags,
1480         .move = &amdgpu_bo_move,
1481         .verify_access = &amdgpu_verify_access,
1482         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1483         .release_notify = &amdgpu_bo_release_notify,
1484         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1485         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1486         .access_memory = &amdgpu_ttm_access_memory,
1487         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1488 };
1489
1490 /*
1491  * Firmware Reservation functions
1492  */
1493 /**
1494  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1495  *
1496  * @adev: amdgpu_device pointer
1497  *
1498  * free fw reserved vram if it has been reserved.
1499  */
1500 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1501 {
1502         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1503                 NULL, &adev->mman.fw_vram_usage_va);
1504 }
1505
1506 /**
1507  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1508  *
1509  * @adev: amdgpu_device pointer
1510  *
1511  * create bo vram reservation from fw.
1512  */
1513 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1514 {
1515         uint64_t vram_size = adev->gmc.visible_vram_size;
1516
1517         adev->mman.fw_vram_usage_va = NULL;
1518         adev->mman.fw_vram_usage_reserved_bo = NULL;
1519
1520         if (adev->mman.fw_vram_usage_size == 0 ||
1521             adev->mman.fw_vram_usage_size > vram_size)
1522                 return 0;
1523
1524         return amdgpu_bo_create_kernel_at(adev,
1525                                           adev->mman.fw_vram_usage_start_offset,
1526                                           adev->mman.fw_vram_usage_size,
1527                                           AMDGPU_GEM_DOMAIN_VRAM,
1528                                           &adev->mman.fw_vram_usage_reserved_bo,
1529                                           &adev->mman.fw_vram_usage_va);
1530 }
1531
1532 /*
1533  * Memoy training reservation functions
1534  */
1535
1536 /**
1537  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1538  *
1539  * @adev: amdgpu_device pointer
1540  *
1541  * free memory training reserved vram if it has been reserved.
1542  */
1543 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1544 {
1545         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1546
1547         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1548         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1549         ctx->c2p_bo = NULL;
1550
1551         return 0;
1552 }
1553
1554 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1555 {
1556         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1557
1558         memset(ctx, 0, sizeof(*ctx));
1559
1560         ctx->c2p_train_data_offset =
1561                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1562         ctx->p2c_train_data_offset =
1563                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1564         ctx->train_data_size =
1565                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1566
1567         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1568                         ctx->train_data_size,
1569                         ctx->p2c_train_data_offset,
1570                         ctx->c2p_train_data_offset);
1571 }
1572
1573 /*
1574  * reserve TMR memory at the top of VRAM which holds
1575  * IP Discovery data and is protected by PSP.
1576  */
1577 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1578 {
1579         int ret;
1580         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1581         bool mem_train_support = false;
1582
1583         if (!amdgpu_sriov_vf(adev)) {
1584                 ret = amdgpu_mem_train_support(adev);
1585                 if (ret == 1)
1586                         mem_train_support = true;
1587                 else if (ret == -1)
1588                         return -EINVAL;
1589                 else
1590                         DRM_DEBUG("memory training does not support!\n");
1591         }
1592
1593         /*
1594          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1595          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1596          *
1597          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1598          * discovery data and G6 memory training data respectively
1599          */
1600         adev->mman.discovery_tmr_size =
1601                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1602         if (!adev->mman.discovery_tmr_size)
1603                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1604
1605         if (mem_train_support) {
1606                 /* reserve vram for mem train according to TMR location */
1607                 amdgpu_ttm_training_data_block_init(adev);
1608                 ret = amdgpu_bo_create_kernel_at(adev,
1609                                          ctx->c2p_train_data_offset,
1610                                          ctx->train_data_size,
1611                                          AMDGPU_GEM_DOMAIN_VRAM,
1612                                          &ctx->c2p_bo,
1613                                          NULL);
1614                 if (ret) {
1615                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1616                         amdgpu_ttm_training_reserve_vram_fini(adev);
1617                         return ret;
1618                 }
1619                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1620         }
1621
1622         ret = amdgpu_bo_create_kernel_at(adev,
1623                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1624                                 adev->mman.discovery_tmr_size,
1625                                 AMDGPU_GEM_DOMAIN_VRAM,
1626                                 &adev->mman.discovery_memory,
1627                                 NULL);
1628         if (ret) {
1629                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1630                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1631                 return ret;
1632         }
1633
1634         return 0;
1635 }
1636
1637 /*
1638  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1639  * gtt/vram related fields.
1640  *
1641  * This initializes all of the memory space pools that the TTM layer
1642  * will need such as the GTT space (system memory mapped to the device),
1643  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1644  * can be mapped per VMID.
1645  */
1646 int amdgpu_ttm_init(struct amdgpu_device *adev)
1647 {
1648         uint64_t gtt_size;
1649         int r;
1650         u64 vis_vram_limit;
1651
1652         mutex_init(&adev->mman.gtt_window_lock);
1653
1654         /* No others user of address space so set it to 0 */
1655         r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1656                                adev_to_drm(adev)->anon_inode->i_mapping,
1657                                adev_to_drm(adev)->vma_offset_manager,
1658                                adev->need_swiotlb,
1659                                dma_addressing_limited(adev->dev));
1660         if (r) {
1661                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1662                 return r;
1663         }
1664         adev->mman.initialized = true;
1665
1666         /* Initialize VRAM pool with all of VRAM divided into pages */
1667         r = amdgpu_vram_mgr_init(adev);
1668         if (r) {
1669                 DRM_ERROR("Failed initializing VRAM heap.\n");
1670                 return r;
1671         }
1672
1673         /* Reduce size of CPU-visible VRAM if requested */
1674         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1675         if (amdgpu_vis_vram_limit > 0 &&
1676             vis_vram_limit <= adev->gmc.visible_vram_size)
1677                 adev->gmc.visible_vram_size = vis_vram_limit;
1678
1679         /* Change the size here instead of the init above so only lpfn is affected */
1680         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1681 #ifdef CONFIG_64BIT
1682 #ifdef CONFIG_X86
1683         if (adev->gmc.xgmi.connected_to_cpu)
1684                 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1685                                 adev->gmc.visible_vram_size);
1686
1687         else
1688 #endif
1689                 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1690                                 adev->gmc.visible_vram_size);
1691 #endif
1692
1693         /*
1694          *The reserved vram for firmware must be pinned to the specified
1695          *place on the VRAM, so reserve it early.
1696          */
1697         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1698         if (r) {
1699                 return r;
1700         }
1701
1702         /*
1703          * only NAVI10 and onwards ASIC support for IP discovery.
1704          * If IP discovery enabled, a block of memory should be
1705          * reserved for IP discovey.
1706          */
1707         if (adev->mman.discovery_bin) {
1708                 r = amdgpu_ttm_reserve_tmr(adev);
1709                 if (r)
1710                         return r;
1711         }
1712
1713         /* allocate memory as required for VGA
1714          * This is used for VGA emulation and pre-OS scanout buffers to
1715          * avoid display artifacts while transitioning between pre-OS
1716          * and driver.  */
1717         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1718                                        AMDGPU_GEM_DOMAIN_VRAM,
1719                                        &adev->mman.stolen_vga_memory,
1720                                        NULL);
1721         if (r)
1722                 return r;
1723         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1724                                        adev->mman.stolen_extended_size,
1725                                        AMDGPU_GEM_DOMAIN_VRAM,
1726                                        &adev->mman.stolen_extended_memory,
1727                                        NULL);
1728         if (r)
1729                 return r;
1730
1731         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1732                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1733
1734         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1735          * or whatever the user passed on module init */
1736         if (amdgpu_gtt_size == -1) {
1737                 struct sysinfo si;
1738
1739                 si_meminfo(&si);
1740                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1741                                adev->gmc.mc_vram_size),
1742                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1743         }
1744         else
1745                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1746
1747         /* Initialize GTT memory pool */
1748         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1749         if (r) {
1750                 DRM_ERROR("Failed initializing GTT heap.\n");
1751                 return r;
1752         }
1753         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1754                  (unsigned)(gtt_size / (1024 * 1024)));
1755
1756         /* Initialize various on-chip memory pools */
1757         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1758         if (r) {
1759                 DRM_ERROR("Failed initializing GDS heap.\n");
1760                 return r;
1761         }
1762
1763         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1764         if (r) {
1765                 DRM_ERROR("Failed initializing gws heap.\n");
1766                 return r;
1767         }
1768
1769         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1770         if (r) {
1771                 DRM_ERROR("Failed initializing oa heap.\n");
1772                 return r;
1773         }
1774
1775         return 0;
1776 }
1777
1778 /*
1779  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1780  */
1781 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1782 {
1783         if (!adev->mman.initialized)
1784                 return;
1785
1786         amdgpu_ttm_training_reserve_vram_fini(adev);
1787         /* return the stolen vga memory back to VRAM */
1788         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1789         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1790         /* return the IP Discovery TMR memory back to VRAM */
1791         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1792         amdgpu_ttm_fw_reserve_vram_fini(adev);
1793
1794         if (adev->mman.aper_base_kaddr)
1795                 iounmap(adev->mman.aper_base_kaddr);
1796         adev->mman.aper_base_kaddr = NULL;
1797
1798         amdgpu_vram_mgr_fini(adev);
1799         amdgpu_gtt_mgr_fini(adev);
1800         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1801         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1802         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1803         ttm_device_fini(&adev->mman.bdev);
1804         adev->mman.initialized = false;
1805         DRM_INFO("amdgpu: ttm finalized\n");
1806 }
1807
1808 /**
1809  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1810  *
1811  * @adev: amdgpu_device pointer
1812  * @enable: true when we can use buffer functions.
1813  *
1814  * Enable/disable use of buffer functions during suspend/resume. This should
1815  * only be called at bootup or when userspace isn't running.
1816  */
1817 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1818 {
1819         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1820         uint64_t size;
1821         int r;
1822
1823         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1824             adev->mman.buffer_funcs_enabled == enable)
1825                 return;
1826
1827         if (enable) {
1828                 struct amdgpu_ring *ring;
1829                 struct drm_gpu_scheduler *sched;
1830
1831                 ring = adev->mman.buffer_funcs_ring;
1832                 sched = &ring->sched;
1833                 r = drm_sched_entity_init(&adev->mman.entity,
1834                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1835                                           1, NULL);
1836                 if (r) {
1837                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1838                                   r);
1839                         return;
1840                 }
1841         } else {
1842                 drm_sched_entity_destroy(&adev->mman.entity);
1843                 dma_fence_put(man->move);
1844                 man->move = NULL;
1845         }
1846
1847         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1848         if (enable)
1849                 size = adev->gmc.real_vram_size;
1850         else
1851                 size = adev->gmc.visible_vram_size;
1852         man->size = size >> PAGE_SHIFT;
1853         adev->mman.buffer_funcs_enabled = enable;
1854 }
1855
1856 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
1857 {
1858         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
1859         vm_fault_t ret;
1860
1861         ret = ttm_bo_vm_reserve(bo, vmf);
1862         if (ret)
1863                 return ret;
1864
1865         ret = amdgpu_bo_fault_reserve_notify(bo);
1866         if (ret)
1867                 goto unlock;
1868
1869         ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
1870                                        TTM_BO_VM_NUM_PREFAULT, 1);
1871         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
1872                 return ret;
1873
1874 unlock:
1875         dma_resv_unlock(bo->base.resv);
1876         return ret;
1877 }
1878
1879 static const struct vm_operations_struct amdgpu_ttm_vm_ops = {
1880         .fault = amdgpu_ttm_fault,
1881         .open = ttm_bo_vm_open,
1882         .close = ttm_bo_vm_close,
1883         .access = ttm_bo_vm_access
1884 };
1885
1886 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1887 {
1888         struct drm_file *file_priv = filp->private_data;
1889         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
1890         int r;
1891
1892         r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1893         if (unlikely(r != 0))
1894                 return r;
1895
1896         vma->vm_ops = &amdgpu_ttm_vm_ops;
1897         return 0;
1898 }
1899
1900 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1901                        uint64_t dst_offset, uint32_t byte_count,
1902                        struct dma_resv *resv,
1903                        struct dma_fence **fence, bool direct_submit,
1904                        bool vm_needs_flush, bool tmz)
1905 {
1906         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
1907                 AMDGPU_IB_POOL_DELAYED;
1908         struct amdgpu_device *adev = ring->adev;
1909         struct amdgpu_job *job;
1910
1911         uint32_t max_bytes;
1912         unsigned num_loops, num_dw;
1913         unsigned i;
1914         int r;
1915
1916         if (direct_submit && !ring->sched.ready) {
1917                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1918                 return -EINVAL;
1919         }
1920
1921         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1922         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1923         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
1924
1925         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
1926         if (r)
1927                 return r;
1928
1929         if (vm_needs_flush) {
1930                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1931                                         adev->gmc.pdb0_bo : adev->gart.bo);
1932                 job->vm_needs_flush = true;
1933         }
1934         if (resv) {
1935                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1936                                      AMDGPU_SYNC_ALWAYS,
1937                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1938                 if (r) {
1939                         DRM_ERROR("sync failed (%d).\n", r);
1940                         goto error_free;
1941                 }
1942         }
1943
1944         for (i = 0; i < num_loops; i++) {
1945                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1946
1947                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1948                                         dst_offset, cur_size_in_bytes, tmz);
1949
1950                 src_offset += cur_size_in_bytes;
1951                 dst_offset += cur_size_in_bytes;
1952                 byte_count -= cur_size_in_bytes;
1953         }
1954
1955         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1956         WARN_ON(job->ibs[0].length_dw > num_dw);
1957         if (direct_submit)
1958                 r = amdgpu_job_submit_direct(job, ring, fence);
1959         else
1960                 r = amdgpu_job_submit(job, &adev->mman.entity,
1961                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1962         if (r)
1963                 goto error_free;
1964
1965         return r;
1966
1967 error_free:
1968         amdgpu_job_free(job);
1969         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1970         return r;
1971 }
1972
1973 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1974                        uint32_t src_data,
1975                        struct dma_resv *resv,
1976                        struct dma_fence **fence)
1977 {
1978         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1979         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1980         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1981
1982         struct amdgpu_res_cursor cursor;
1983         unsigned int num_loops, num_dw;
1984         uint64_t num_bytes;
1985
1986         struct amdgpu_job *job;
1987         int r;
1988
1989         if (!adev->mman.buffer_funcs_enabled) {
1990                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1991                 return -EINVAL;
1992         }
1993
1994         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1995                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1996                 if (r)
1997                         return r;
1998         }
1999
2000         num_bytes = bo->tbo.mem.num_pages << PAGE_SHIFT;
2001         num_loops = 0;
2002
2003         amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor);
2004         while (cursor.remaining) {
2005                 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes);
2006                 amdgpu_res_next(&cursor, cursor.size);
2007         }
2008         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2009
2010         /* for IB padding */
2011         num_dw += 64;
2012
2013         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2014                                      &job);
2015         if (r)
2016                 return r;
2017
2018         if (resv) {
2019                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2020                                      AMDGPU_SYNC_ALWAYS,
2021                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2022                 if (r) {
2023                         DRM_ERROR("sync failed (%d).\n", r);
2024                         goto error_free;
2025                 }
2026         }
2027
2028         amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor);
2029         while (cursor.remaining) {
2030                 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes);
2031                 uint64_t dst_addr = cursor.start;
2032
2033                 dst_addr += amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type);
2034                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2035                                         cur_size);
2036
2037                 amdgpu_res_next(&cursor, cur_size);
2038         }
2039
2040         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2041         WARN_ON(job->ibs[0].length_dw > num_dw);
2042         r = amdgpu_job_submit(job, &adev->mman.entity,
2043                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2044         if (r)
2045                 goto error_free;
2046
2047         return 0;
2048
2049 error_free:
2050         amdgpu_job_free(job);
2051         return r;
2052 }
2053
2054 #if defined(CONFIG_DEBUG_FS)
2055
2056 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused)
2057 {
2058         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2059         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2060                                                             TTM_PL_VRAM);
2061         struct drm_printer p = drm_seq_file_printer(m);
2062
2063         man->func->debug(man, &p);
2064         return 0;
2065 }
2066
2067 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2068 {
2069         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2070
2071         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2072 }
2073
2074 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused)
2075 {
2076         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2077         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2078                                                             TTM_PL_TT);
2079         struct drm_printer p = drm_seq_file_printer(m);
2080
2081         man->func->debug(man, &p);
2082         return 0;
2083 }
2084
2085 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused)
2086 {
2087         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2088         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2089                                                             AMDGPU_PL_GDS);
2090         struct drm_printer p = drm_seq_file_printer(m);
2091
2092         man->func->debug(man, &p);
2093         return 0;
2094 }
2095
2096 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused)
2097 {
2098         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2099         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2100                                                             AMDGPU_PL_GWS);
2101         struct drm_printer p = drm_seq_file_printer(m);
2102
2103         man->func->debug(man, &p);
2104         return 0;
2105 }
2106
2107 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused)
2108 {
2109         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2110         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2111                                                             AMDGPU_PL_OA);
2112         struct drm_printer p = drm_seq_file_printer(m);
2113
2114         man->func->debug(man, &p);
2115         return 0;
2116 }
2117
2118 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table);
2119 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table);
2120 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table);
2121 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table);
2122 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table);
2123 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2124
2125 /*
2126  * amdgpu_ttm_vram_read - Linear read access to VRAM
2127  *
2128  * Accesses VRAM via MMIO for debugging purposes.
2129  */
2130 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2131                                     size_t size, loff_t *pos)
2132 {
2133         struct amdgpu_device *adev = file_inode(f)->i_private;
2134         ssize_t result = 0;
2135
2136         if (size & 0x3 || *pos & 0x3)
2137                 return -EINVAL;
2138
2139         if (*pos >= adev->gmc.mc_vram_size)
2140                 return -ENXIO;
2141
2142         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2143         while (size) {
2144                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2145                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2146
2147                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2148                 if (copy_to_user(buf, value, bytes))
2149                         return -EFAULT;
2150
2151                 result += bytes;
2152                 buf += bytes;
2153                 *pos += bytes;
2154                 size -= bytes;
2155         }
2156
2157         return result;
2158 }
2159
2160 /*
2161  * amdgpu_ttm_vram_write - Linear write access to VRAM
2162  *
2163  * Accesses VRAM via MMIO for debugging purposes.
2164  */
2165 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2166                                     size_t size, loff_t *pos)
2167 {
2168         struct amdgpu_device *adev = file_inode(f)->i_private;
2169         ssize_t result = 0;
2170         int r;
2171
2172         if (size & 0x3 || *pos & 0x3)
2173                 return -EINVAL;
2174
2175         if (*pos >= adev->gmc.mc_vram_size)
2176                 return -ENXIO;
2177
2178         while (size) {
2179                 unsigned long flags;
2180                 uint32_t value;
2181
2182                 if (*pos >= adev->gmc.mc_vram_size)
2183                         return result;
2184
2185                 r = get_user(value, (uint32_t *)buf);
2186                 if (r)
2187                         return r;
2188
2189                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2190                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2191                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2192                 WREG32_NO_KIQ(mmMM_DATA, value);
2193                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2194
2195                 result += 4;
2196                 buf += 4;
2197                 *pos += 4;
2198                 size -= 4;
2199         }
2200
2201         return result;
2202 }
2203
2204 static const struct file_operations amdgpu_ttm_vram_fops = {
2205         .owner = THIS_MODULE,
2206         .read = amdgpu_ttm_vram_read,
2207         .write = amdgpu_ttm_vram_write,
2208         .llseek = default_llseek,
2209 };
2210
2211 /*
2212  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2213  *
2214  * This function is used to read memory that has been mapped to the
2215  * GPU and the known addresses are not physical addresses but instead
2216  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2217  */
2218 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2219                                  size_t size, loff_t *pos)
2220 {
2221         struct amdgpu_device *adev = file_inode(f)->i_private;
2222         struct iommu_domain *dom;
2223         ssize_t result = 0;
2224         int r;
2225
2226         /* retrieve the IOMMU domain if any for this device */
2227         dom = iommu_get_domain_for_dev(adev->dev);
2228
2229         while (size) {
2230                 phys_addr_t addr = *pos & PAGE_MASK;
2231                 loff_t off = *pos & ~PAGE_MASK;
2232                 size_t bytes = PAGE_SIZE - off;
2233                 unsigned long pfn;
2234                 struct page *p;
2235                 void *ptr;
2236
2237                 bytes = bytes < size ? bytes : size;
2238
2239                 /* Translate the bus address to a physical address.  If
2240                  * the domain is NULL it means there is no IOMMU active
2241                  * and the address translation is the identity
2242                  */
2243                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2244
2245                 pfn = addr >> PAGE_SHIFT;
2246                 if (!pfn_valid(pfn))
2247                         return -EPERM;
2248
2249                 p = pfn_to_page(pfn);
2250                 if (p->mapping != adev->mman.bdev.dev_mapping)
2251                         return -EPERM;
2252
2253                 ptr = kmap(p);
2254                 r = copy_to_user(buf, ptr + off, bytes);
2255                 kunmap(p);
2256                 if (r)
2257                         return -EFAULT;
2258
2259                 size -= bytes;
2260                 *pos += bytes;
2261                 result += bytes;
2262         }
2263
2264         return result;
2265 }
2266
2267 /*
2268  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2269  *
2270  * This function is used to write memory that has been mapped to the
2271  * GPU and the known addresses are not physical addresses but instead
2272  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2273  */
2274 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2275                                  size_t size, loff_t *pos)
2276 {
2277         struct amdgpu_device *adev = file_inode(f)->i_private;
2278         struct iommu_domain *dom;
2279         ssize_t result = 0;
2280         int r;
2281
2282         dom = iommu_get_domain_for_dev(adev->dev);
2283
2284         while (size) {
2285                 phys_addr_t addr = *pos & PAGE_MASK;
2286                 loff_t off = *pos & ~PAGE_MASK;
2287                 size_t bytes = PAGE_SIZE - off;
2288                 unsigned long pfn;
2289                 struct page *p;
2290                 void *ptr;
2291
2292                 bytes = bytes < size ? bytes : size;
2293
2294                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2295
2296                 pfn = addr >> PAGE_SHIFT;
2297                 if (!pfn_valid(pfn))
2298                         return -EPERM;
2299
2300                 p = pfn_to_page(pfn);
2301                 if (p->mapping != adev->mman.bdev.dev_mapping)
2302                         return -EPERM;
2303
2304                 ptr = kmap(p);
2305                 r = copy_from_user(ptr + off, buf, bytes);
2306                 kunmap(p);
2307                 if (r)
2308                         return -EFAULT;
2309
2310                 size -= bytes;
2311                 *pos += bytes;
2312                 result += bytes;
2313         }
2314
2315         return result;
2316 }
2317
2318 static const struct file_operations amdgpu_ttm_iomem_fops = {
2319         .owner = THIS_MODULE,
2320         .read = amdgpu_iomem_read,
2321         .write = amdgpu_iomem_write,
2322         .llseek = default_llseek
2323 };
2324
2325 #endif
2326
2327 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2328 {
2329 #if defined(CONFIG_DEBUG_FS)
2330         struct drm_minor *minor = adev_to_drm(adev)->primary;
2331         struct dentry *root = minor->debugfs_root;
2332
2333         debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2334                                  &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2335         debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2336                             &amdgpu_ttm_iomem_fops);
2337         debugfs_create_file("amdgpu_vram_mm", 0444, root, adev,
2338                             &amdgpu_mm_vram_table_fops);
2339         debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev,
2340                             &amdgpu_mm_tt_table_fops);
2341         debugfs_create_file("amdgpu_gds_mm", 0444, root, adev,
2342                             &amdgpu_mm_gds_table_fops);
2343         debugfs_create_file("amdgpu_gws_mm", 0444, root, adev,
2344                             &amdgpu_mm_gws_table_fops);
2345         debugfs_create_file("amdgpu_oa_mm", 0444, root, adev,
2346                             &amdgpu_mm_oa_table_fops);
2347         debugfs_create_file("ttm_page_pool", 0444, root, adev,
2348                             &amdgpu_ttm_page_pool_fops);
2349 #endif
2350 }