2 * Hardware modules present on the DRA7xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod.h"
31 #include "omap_hwmod_common_data.h"
40 /* Base offset for all DRA7XX interrupts external to MPUSS */
41 #define DRA7XX_IRQ_GIC_START 32
43 /* Base offset for all DRA7XX dma requests */
44 #define DRA7XX_DMA_REQ_START 1
53 * instance(s): l3_instr, l3_main_1, l3_main_2
55 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
60 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
62 .class = &dra7xx_l3_hwmod_class,
63 .clkdm_name = "l3instr_clkdm",
66 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
68 .modulemode = MODULEMODE_HWCTRL,
74 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
76 .class = &dra7xx_l3_hwmod_class,
77 .clkdm_name = "l3main1_clkdm",
80 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
81 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
87 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
89 .class = &dra7xx_l3_hwmod_class,
90 .clkdm_name = "l3instr_clkdm",
93 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
94 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
95 .modulemode = MODULEMODE_HWCTRL,
102 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
104 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
109 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
111 .class = &dra7xx_l4_hwmod_class,
112 .clkdm_name = "l4cfg_clkdm",
115 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
116 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
122 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
124 .class = &dra7xx_l4_hwmod_class,
125 .clkdm_name = "l4per_clkdm",
128 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
129 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
135 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
137 .class = &dra7xx_l4_hwmod_class,
138 .clkdm_name = "l4per2_clkdm",
141 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
142 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
148 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
150 .class = &dra7xx_l4_hwmod_class,
151 .clkdm_name = "l4per3_clkdm",
154 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
155 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
161 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
163 .class = &dra7xx_l4_hwmod_class,
164 .clkdm_name = "wkupaon_clkdm",
167 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
168 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
178 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
183 static struct omap_hwmod dra7xx_atl_hwmod = {
185 .class = &dra7xx_atl_hwmod_class,
186 .clkdm_name = "atl_clkdm",
187 .main_clk = "atl_gfclk_mux",
190 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
191 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
192 .modulemode = MODULEMODE_SWCTRL,
202 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
207 static struct omap_hwmod dra7xx_bb2d_hwmod = {
209 .class = &dra7xx_bb2d_hwmod_class,
210 .clkdm_name = "dss_clkdm",
211 .main_clk = "dpll_core_h24x2_ck",
214 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
215 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
216 .modulemode = MODULEMODE_SWCTRL,
226 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
229 .sysc_flags = SYSC_HAS_SIDLEMODE,
230 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
232 .sysc_fields = &omap_hwmod_sysc_type1,
235 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
237 .sysc = &dra7xx_counter_sysc,
241 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
242 .name = "counter_32k",
243 .class = &dra7xx_counter_hwmod_class,
244 .clkdm_name = "wkupaon_clkdm",
245 .flags = HWMOD_SWSUP_SIDLE,
246 .main_clk = "wkupaon_iclk_mux",
249 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
250 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
256 * 'ctrl_module' class
260 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
261 .name = "ctrl_module",
264 /* ctrl_module_wkup */
265 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
266 .name = "ctrl_module_wkup",
267 .class = &dra7xx_ctrl_module_hwmod_class,
268 .clkdm_name = "wkupaon_clkdm",
271 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
278 * cpsw/gmac sub system
280 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
284 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
285 SYSS_HAS_RESET_STATUS),
286 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
288 .sysc_fields = &omap_hwmod_sysc_type3,
291 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
293 .sysc = &dra7xx_gmac_sysc,
296 static struct omap_hwmod dra7xx_gmac_hwmod = {
298 .class = &dra7xx_gmac_hwmod_class,
299 .clkdm_name = "gmac_clkdm",
300 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
301 .main_clk = "dpll_gmac_ck",
305 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
306 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
307 .modulemode = MODULEMODE_SWCTRL,
315 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
316 .name = "davinci_mdio",
319 static struct omap_hwmod dra7xx_mdio_hwmod = {
320 .name = "davinci_mdio",
321 .class = &dra7xx_mdio_hwmod_class,
322 .clkdm_name = "gmac_clkdm",
323 .main_clk = "dpll_gmac_ck",
331 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
336 static struct omap_hwmod dra7xx_dcan1_hwmod = {
338 .class = &dra7xx_dcan_hwmod_class,
339 .clkdm_name = "wkupaon_clkdm",
340 .main_clk = "dcan1_sys_clk_mux",
343 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
344 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
345 .modulemode = MODULEMODE_SWCTRL,
351 static struct omap_hwmod dra7xx_dcan2_hwmod = {
353 .class = &dra7xx_dcan_hwmod_class,
354 .clkdm_name = "l4per2_clkdm",
355 .main_clk = "sys_clkin1",
358 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
359 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
360 .modulemode = MODULEMODE_SWCTRL,
370 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
374 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
375 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
376 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
377 SYSS_HAS_RESET_STATUS),
378 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
379 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
380 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
381 .sysc_fields = &omap_hwmod_sysc_type1,
384 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
386 .sysc = &dra7xx_dma_sysc,
390 static struct omap_dma_dev_attr dma_dev_attr = {
391 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
392 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
397 static struct omap_hwmod dra7xx_dma_system_hwmod = {
398 .name = "dma_system",
399 .class = &dra7xx_dma_hwmod_class,
400 .clkdm_name = "dma_clkdm",
401 .main_clk = "l3_iclk_div",
404 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
405 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
408 .dev_attr = &dma_dev_attr,
416 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
419 .sysc_flags = SYSS_HAS_RESET_STATUS,
422 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
424 .sysc = &dra7xx_dss_sysc,
425 .reset = omap_dss_reset,
429 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
430 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
434 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
435 { .role = "dss_clk", .clk = "dss_dss_clk" },
436 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
437 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
438 { .role = "video2_clk", .clk = "dss_video2_clk" },
439 { .role = "video1_clk", .clk = "dss_video1_clk" },
440 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
443 static struct omap_hwmod dra7xx_dss_hwmod = {
445 .class = &dra7xx_dss_hwmod_class,
446 .clkdm_name = "dss_clkdm",
447 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
448 .sdma_reqs = dra7xx_dss_sdma_reqs,
449 .main_clk = "dss_dss_clk",
452 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
453 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
454 .modulemode = MODULEMODE_SWCTRL,
457 .opt_clks = dss_opt_clks,
458 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
466 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
470 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
471 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
472 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
473 SYSS_HAS_RESET_STATUS),
474 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
475 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
476 .sysc_fields = &omap_hwmod_sysc_type1,
479 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
481 .sysc = &dra7xx_dispc_sysc,
485 /* dss_dispc dev_attr */
486 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
487 .has_framedonetv_irq = 1,
491 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
493 .class = &dra7xx_dispc_hwmod_class,
494 .clkdm_name = "dss_clkdm",
495 .main_clk = "dss_dss_clk",
498 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
499 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
502 .dev_attr = &dss_dispc_dev_attr,
510 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
513 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
515 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
517 .sysc_fields = &omap_hwmod_sysc_type2,
520 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
522 .sysc = &dra7xx_hdmi_sysc,
527 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
528 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
531 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
533 .class = &dra7xx_hdmi_hwmod_class,
534 .clkdm_name = "dss_clkdm",
535 .main_clk = "dss_48mhz_clk",
538 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
539 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
542 .opt_clks = dss_hdmi_opt_clks,
543 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
551 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
555 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
556 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
557 SYSS_HAS_RESET_STATUS),
558 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
560 .sysc_fields = &omap_hwmod_sysc_type1,
563 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
565 .sysc = &dra7xx_elm_sysc,
570 static struct omap_hwmod dra7xx_elm_hwmod = {
572 .class = &dra7xx_elm_hwmod_class,
573 .clkdm_name = "l4per_clkdm",
574 .main_clk = "l3_iclk_div",
577 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
578 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
588 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
592 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
593 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
594 SYSS_HAS_RESET_STATUS),
595 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
597 .sysc_fields = &omap_hwmod_sysc_type1,
600 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
602 .sysc = &dra7xx_gpio_sysc,
607 static struct omap_gpio_dev_attr gpio_dev_attr = {
613 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
614 { .role = "dbclk", .clk = "gpio1_dbclk" },
617 static struct omap_hwmod dra7xx_gpio1_hwmod = {
619 .class = &dra7xx_gpio_hwmod_class,
620 .clkdm_name = "wkupaon_clkdm",
621 .main_clk = "wkupaon_iclk_mux",
624 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
625 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
626 .modulemode = MODULEMODE_HWCTRL,
629 .opt_clks = gpio1_opt_clks,
630 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
631 .dev_attr = &gpio_dev_attr,
635 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
636 { .role = "dbclk", .clk = "gpio2_dbclk" },
639 static struct omap_hwmod dra7xx_gpio2_hwmod = {
641 .class = &dra7xx_gpio_hwmod_class,
642 .clkdm_name = "l4per_clkdm",
643 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
644 .main_clk = "l3_iclk_div",
647 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
648 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
649 .modulemode = MODULEMODE_HWCTRL,
652 .opt_clks = gpio2_opt_clks,
653 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
654 .dev_attr = &gpio_dev_attr,
658 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
659 { .role = "dbclk", .clk = "gpio3_dbclk" },
662 static struct omap_hwmod dra7xx_gpio3_hwmod = {
664 .class = &dra7xx_gpio_hwmod_class,
665 .clkdm_name = "l4per_clkdm",
666 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
667 .main_clk = "l3_iclk_div",
670 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
671 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
672 .modulemode = MODULEMODE_HWCTRL,
675 .opt_clks = gpio3_opt_clks,
676 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
677 .dev_attr = &gpio_dev_attr,
681 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
682 { .role = "dbclk", .clk = "gpio4_dbclk" },
685 static struct omap_hwmod dra7xx_gpio4_hwmod = {
687 .class = &dra7xx_gpio_hwmod_class,
688 .clkdm_name = "l4per_clkdm",
689 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
690 .main_clk = "l3_iclk_div",
693 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
694 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
695 .modulemode = MODULEMODE_HWCTRL,
698 .opt_clks = gpio4_opt_clks,
699 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
700 .dev_attr = &gpio_dev_attr,
704 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
705 { .role = "dbclk", .clk = "gpio5_dbclk" },
708 static struct omap_hwmod dra7xx_gpio5_hwmod = {
710 .class = &dra7xx_gpio_hwmod_class,
711 .clkdm_name = "l4per_clkdm",
712 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
713 .main_clk = "l3_iclk_div",
716 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
717 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
718 .modulemode = MODULEMODE_HWCTRL,
721 .opt_clks = gpio5_opt_clks,
722 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
723 .dev_attr = &gpio_dev_attr,
727 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
728 { .role = "dbclk", .clk = "gpio6_dbclk" },
731 static struct omap_hwmod dra7xx_gpio6_hwmod = {
733 .class = &dra7xx_gpio_hwmod_class,
734 .clkdm_name = "l4per_clkdm",
735 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
736 .main_clk = "l3_iclk_div",
739 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
740 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
741 .modulemode = MODULEMODE_HWCTRL,
744 .opt_clks = gpio6_opt_clks,
745 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
746 .dev_attr = &gpio_dev_attr,
750 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
751 { .role = "dbclk", .clk = "gpio7_dbclk" },
754 static struct omap_hwmod dra7xx_gpio7_hwmod = {
756 .class = &dra7xx_gpio_hwmod_class,
757 .clkdm_name = "l4per_clkdm",
758 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
759 .main_clk = "l3_iclk_div",
762 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
763 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
764 .modulemode = MODULEMODE_HWCTRL,
767 .opt_clks = gpio7_opt_clks,
768 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
769 .dev_attr = &gpio_dev_attr,
773 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
774 { .role = "dbclk", .clk = "gpio8_dbclk" },
777 static struct omap_hwmod dra7xx_gpio8_hwmod = {
779 .class = &dra7xx_gpio_hwmod_class,
780 .clkdm_name = "l4per_clkdm",
781 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
782 .main_clk = "l3_iclk_div",
785 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
786 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
787 .modulemode = MODULEMODE_HWCTRL,
790 .opt_clks = gpio8_opt_clks,
791 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
792 .dev_attr = &gpio_dev_attr,
800 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
804 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
805 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
806 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
808 .sysc_fields = &omap_hwmod_sysc_type1,
811 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
813 .sysc = &dra7xx_gpmc_sysc,
818 static struct omap_hwmod dra7xx_gpmc_hwmod = {
820 .class = &dra7xx_gpmc_hwmod_class,
821 .clkdm_name = "l3main1_clkdm",
822 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
823 .main_clk = "l3_iclk_div",
826 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
827 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
828 .modulemode = MODULEMODE_HWCTRL,
838 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
842 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
843 SYSS_HAS_RESET_STATUS),
844 .sysc_fields = &omap_hwmod_sysc_type1,
847 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
849 .sysc = &dra7xx_hdq1w_sysc,
854 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
856 .class = &dra7xx_hdq1w_hwmod_class,
857 .clkdm_name = "l4per_clkdm",
858 .flags = HWMOD_INIT_NO_RESET,
859 .main_clk = "func_12m_fclk",
862 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
863 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
864 .modulemode = MODULEMODE_SWCTRL,
874 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
877 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
878 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
879 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
880 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
882 .clockact = CLOCKACT_TEST_ICLK,
883 .sysc_fields = &omap_hwmod_sysc_type1,
886 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
888 .sysc = &dra7xx_i2c_sysc,
889 .reset = &omap_i2c_reset,
890 .rev = OMAP_I2C_IP_VERSION_2,
894 static struct omap_i2c_dev_attr i2c_dev_attr = {
895 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
899 static struct omap_hwmod dra7xx_i2c1_hwmod = {
901 .class = &dra7xx_i2c_hwmod_class,
902 .clkdm_name = "l4per_clkdm",
903 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
904 .main_clk = "func_96m_fclk",
907 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
908 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
909 .modulemode = MODULEMODE_SWCTRL,
912 .dev_attr = &i2c_dev_attr,
916 static struct omap_hwmod dra7xx_i2c2_hwmod = {
918 .class = &dra7xx_i2c_hwmod_class,
919 .clkdm_name = "l4per_clkdm",
920 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
921 .main_clk = "func_96m_fclk",
924 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
925 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
926 .modulemode = MODULEMODE_SWCTRL,
929 .dev_attr = &i2c_dev_attr,
933 static struct omap_hwmod dra7xx_i2c3_hwmod = {
935 .class = &dra7xx_i2c_hwmod_class,
936 .clkdm_name = "l4per_clkdm",
937 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
938 .main_clk = "func_96m_fclk",
941 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
942 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
943 .modulemode = MODULEMODE_SWCTRL,
946 .dev_attr = &i2c_dev_attr,
950 static struct omap_hwmod dra7xx_i2c4_hwmod = {
952 .class = &dra7xx_i2c_hwmod_class,
953 .clkdm_name = "l4per_clkdm",
954 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
955 .main_clk = "func_96m_fclk",
958 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
959 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
960 .modulemode = MODULEMODE_SWCTRL,
963 .dev_attr = &i2c_dev_attr,
967 static struct omap_hwmod dra7xx_i2c5_hwmod = {
969 .class = &dra7xx_i2c_hwmod_class,
970 .clkdm_name = "ipu_clkdm",
971 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
972 .main_clk = "func_96m_fclk",
975 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
976 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
977 .modulemode = MODULEMODE_SWCTRL,
980 .dev_attr = &i2c_dev_attr,
988 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
991 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
993 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
994 .sysc_fields = &omap_hwmod_sysc_type2,
997 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
999 .sysc = &dra7xx_mailbox_sysc,
1003 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1005 .class = &dra7xx_mailbox_hwmod_class,
1006 .clkdm_name = "l4cfg_clkdm",
1009 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1010 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1016 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1018 .class = &dra7xx_mailbox_hwmod_class,
1019 .clkdm_name = "l4cfg_clkdm",
1022 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1023 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1029 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1031 .class = &dra7xx_mailbox_hwmod_class,
1032 .clkdm_name = "l4cfg_clkdm",
1035 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1036 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1042 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1044 .class = &dra7xx_mailbox_hwmod_class,
1045 .clkdm_name = "l4cfg_clkdm",
1048 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1049 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1055 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1057 .class = &dra7xx_mailbox_hwmod_class,
1058 .clkdm_name = "l4cfg_clkdm",
1061 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1062 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1068 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1070 .class = &dra7xx_mailbox_hwmod_class,
1071 .clkdm_name = "l4cfg_clkdm",
1074 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1075 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1081 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1083 .class = &dra7xx_mailbox_hwmod_class,
1084 .clkdm_name = "l4cfg_clkdm",
1087 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1088 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1094 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1096 .class = &dra7xx_mailbox_hwmod_class,
1097 .clkdm_name = "l4cfg_clkdm",
1100 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1101 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1107 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1109 .class = &dra7xx_mailbox_hwmod_class,
1110 .clkdm_name = "l4cfg_clkdm",
1113 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1114 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1120 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1121 .name = "mailbox10",
1122 .class = &dra7xx_mailbox_hwmod_class,
1123 .clkdm_name = "l4cfg_clkdm",
1126 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1127 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1133 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1134 .name = "mailbox11",
1135 .class = &dra7xx_mailbox_hwmod_class,
1136 .clkdm_name = "l4cfg_clkdm",
1139 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1140 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1146 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1147 .name = "mailbox12",
1148 .class = &dra7xx_mailbox_hwmod_class,
1149 .clkdm_name = "l4cfg_clkdm",
1152 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1153 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1159 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1160 .name = "mailbox13",
1161 .class = &dra7xx_mailbox_hwmod_class,
1162 .clkdm_name = "l4cfg_clkdm",
1165 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1166 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1176 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1178 .sysc_offs = 0x0010,
1179 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1180 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1181 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1183 .sysc_fields = &omap_hwmod_sysc_type2,
1186 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1188 .sysc = &dra7xx_mcspi_sysc,
1189 .rev = OMAP4_MCSPI_REV,
1193 /* mcspi1 dev_attr */
1194 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1195 .num_chipselect = 4,
1198 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1200 .class = &dra7xx_mcspi_hwmod_class,
1201 .clkdm_name = "l4per_clkdm",
1202 .main_clk = "func_48m_fclk",
1205 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1206 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1207 .modulemode = MODULEMODE_SWCTRL,
1210 .dev_attr = &mcspi1_dev_attr,
1214 /* mcspi2 dev_attr */
1215 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1216 .num_chipselect = 2,
1219 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1221 .class = &dra7xx_mcspi_hwmod_class,
1222 .clkdm_name = "l4per_clkdm",
1223 .main_clk = "func_48m_fclk",
1226 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1227 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1228 .modulemode = MODULEMODE_SWCTRL,
1231 .dev_attr = &mcspi2_dev_attr,
1235 /* mcspi3 dev_attr */
1236 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1237 .num_chipselect = 2,
1240 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1242 .class = &dra7xx_mcspi_hwmod_class,
1243 .clkdm_name = "l4per_clkdm",
1244 .main_clk = "func_48m_fclk",
1247 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1248 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1249 .modulemode = MODULEMODE_SWCTRL,
1252 .dev_attr = &mcspi3_dev_attr,
1256 /* mcspi4 dev_attr */
1257 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1258 .num_chipselect = 1,
1261 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1263 .class = &dra7xx_mcspi_hwmod_class,
1264 .clkdm_name = "l4per_clkdm",
1265 .main_clk = "func_48m_fclk",
1268 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1269 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1270 .modulemode = MODULEMODE_SWCTRL,
1273 .dev_attr = &mcspi4_dev_attr,
1281 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1283 .sysc_offs = 0x0010,
1284 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1285 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1286 SYSC_HAS_SOFTRESET),
1287 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1288 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1289 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1290 .sysc_fields = &omap_hwmod_sysc_type2,
1293 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1295 .sysc = &dra7xx_mmc_sysc,
1299 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1300 { .role = "clk32k", .clk = "mmc1_clk32k" },
1304 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1305 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1308 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1310 .class = &dra7xx_mmc_hwmod_class,
1311 .clkdm_name = "l3init_clkdm",
1312 .main_clk = "mmc1_fclk_div",
1315 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1316 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1317 .modulemode = MODULEMODE_SWCTRL,
1320 .opt_clks = mmc1_opt_clks,
1321 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1322 .dev_attr = &mmc1_dev_attr,
1326 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1327 { .role = "clk32k", .clk = "mmc2_clk32k" },
1330 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1332 .class = &dra7xx_mmc_hwmod_class,
1333 .clkdm_name = "l3init_clkdm",
1334 .main_clk = "mmc2_fclk_div",
1337 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1338 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1339 .modulemode = MODULEMODE_SWCTRL,
1342 .opt_clks = mmc2_opt_clks,
1343 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1347 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1348 { .role = "clk32k", .clk = "mmc3_clk32k" },
1351 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1353 .class = &dra7xx_mmc_hwmod_class,
1354 .clkdm_name = "l4per_clkdm",
1355 .main_clk = "mmc3_gfclk_div",
1358 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1359 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1360 .modulemode = MODULEMODE_SWCTRL,
1363 .opt_clks = mmc3_opt_clks,
1364 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1368 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1369 { .role = "clk32k", .clk = "mmc4_clk32k" },
1372 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1374 .class = &dra7xx_mmc_hwmod_class,
1375 .clkdm_name = "l4per_clkdm",
1376 .main_clk = "mmc4_gfclk_div",
1379 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1380 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1381 .modulemode = MODULEMODE_SWCTRL,
1384 .opt_clks = mmc4_opt_clks,
1385 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1393 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1398 static struct omap_hwmod dra7xx_mpu_hwmod = {
1400 .class = &dra7xx_mpu_hwmod_class,
1401 .clkdm_name = "mpu_clkdm",
1402 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1403 .main_clk = "dpll_mpu_m2_ck",
1406 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1407 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1417 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1419 .sysc_offs = 0x0010,
1420 .syss_offs = 0x0014,
1421 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1422 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1423 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1425 .sysc_fields = &omap_hwmod_sysc_type1,
1428 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1430 .sysc = &dra7xx_ocp2scp_sysc,
1434 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1436 .class = &dra7xx_ocp2scp_hwmod_class,
1437 .clkdm_name = "l3init_clkdm",
1438 .main_clk = "l4_root_clk_div",
1441 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1442 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1443 .modulemode = MODULEMODE_HWCTRL,
1449 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1451 .class = &dra7xx_ocp2scp_hwmod_class,
1452 .clkdm_name = "l3init_clkdm",
1453 .main_clk = "l4_root_clk_div",
1456 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1457 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1458 .modulemode = MODULEMODE_HWCTRL,
1468 static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
1473 static struct omap_hwmod dra7xx_pcie1_hwmod = {
1475 .class = &dra7xx_pcie_hwmod_class,
1476 .clkdm_name = "pcie_clkdm",
1477 .main_clk = "l4_root_clk_div",
1480 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1481 .modulemode = MODULEMODE_SWCTRL,
1487 static struct omap_hwmod dra7xx_pcie2_hwmod = {
1489 .class = &dra7xx_pcie_hwmod_class,
1490 .clkdm_name = "pcie_clkdm",
1491 .main_clk = "l4_root_clk_div",
1494 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1495 .modulemode = MODULEMODE_SWCTRL,
1505 static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
1510 static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
1511 .name = "pcie1-phy",
1512 .class = &dra7xx_pcie_phy_hwmod_class,
1513 .clkdm_name = "l3init_clkdm",
1514 .main_clk = "l4_root_clk_div",
1517 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1518 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1519 .modulemode = MODULEMODE_SWCTRL,
1525 static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
1526 .name = "pcie2-phy",
1527 .class = &dra7xx_pcie_phy_hwmod_class,
1528 .clkdm_name = "l3init_clkdm",
1529 .main_clk = "l4_root_clk_div",
1532 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1533 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1534 .modulemode = MODULEMODE_SWCTRL,
1544 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1545 .sysc_offs = 0x0010,
1546 .sysc_flags = SYSC_HAS_SIDLEMODE,
1547 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1549 .sysc_fields = &omap_hwmod_sysc_type2,
1552 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1554 .sysc = &dra7xx_qspi_sysc,
1558 static struct omap_hwmod dra7xx_qspi_hwmod = {
1560 .class = &dra7xx_qspi_hwmod_class,
1561 .clkdm_name = "l4per2_clkdm",
1562 .main_clk = "qspi_gfclk_div",
1565 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1566 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1567 .modulemode = MODULEMODE_SWCTRL,
1576 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1577 .sysc_offs = 0x0078,
1578 .sysc_flags = SYSC_HAS_SIDLEMODE,
1579 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1581 .sysc_fields = &omap_hwmod_sysc_type3,
1584 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1586 .sysc = &dra7xx_rtcss_sysc,
1590 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1592 .class = &dra7xx_rtcss_hwmod_class,
1593 .clkdm_name = "rtc_clkdm",
1594 .main_clk = "sys_32k_ck",
1597 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1598 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1599 .modulemode = MODULEMODE_SWCTRL,
1609 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1610 .sysc_offs = 0x0000,
1611 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1612 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1613 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1614 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1615 .sysc_fields = &omap_hwmod_sysc_type2,
1618 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1620 .sysc = &dra7xx_sata_sysc,
1625 static struct omap_hwmod dra7xx_sata_hwmod = {
1627 .class = &dra7xx_sata_hwmod_class,
1628 .clkdm_name = "l3init_clkdm",
1629 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1630 .main_clk = "func_48m_fclk",
1634 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1635 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1636 .modulemode = MODULEMODE_SWCTRL,
1642 * 'smartreflex' class
1646 /* The IP is not compliant to type1 / type2 scheme */
1647 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1652 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1653 .sysc_offs = 0x0038,
1654 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1655 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1657 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1660 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1661 .name = "smartreflex",
1662 .sysc = &dra7xx_smartreflex_sysc,
1666 /* smartreflex_core */
1667 /* smartreflex_core dev_attr */
1668 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1669 .sensor_voltdm_name = "core",
1672 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1673 .name = "smartreflex_core",
1674 .class = &dra7xx_smartreflex_hwmod_class,
1675 .clkdm_name = "coreaon_clkdm",
1676 .main_clk = "wkupaon_iclk_mux",
1679 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1680 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1681 .modulemode = MODULEMODE_SWCTRL,
1684 .dev_attr = &smartreflex_core_dev_attr,
1687 /* smartreflex_mpu */
1688 /* smartreflex_mpu dev_attr */
1689 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1690 .sensor_voltdm_name = "mpu",
1693 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1694 .name = "smartreflex_mpu",
1695 .class = &dra7xx_smartreflex_hwmod_class,
1696 .clkdm_name = "coreaon_clkdm",
1697 .main_clk = "wkupaon_iclk_mux",
1700 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1701 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1702 .modulemode = MODULEMODE_SWCTRL,
1705 .dev_attr = &smartreflex_mpu_dev_attr,
1713 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1715 .sysc_offs = 0x0010,
1716 .syss_offs = 0x0014,
1717 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1718 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1719 SYSS_HAS_RESET_STATUS),
1720 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1721 .sysc_fields = &omap_hwmod_sysc_type1,
1724 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1726 .sysc = &dra7xx_spinlock_sysc,
1730 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1732 .class = &dra7xx_spinlock_hwmod_class,
1733 .clkdm_name = "l4cfg_clkdm",
1734 .main_clk = "l3_iclk_div",
1737 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1738 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1746 * This class contains several variants: ['timer_1ms', 'timer_secure',
1750 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1752 .sysc_offs = 0x0010,
1753 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1754 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1755 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1757 .sysc_fields = &omap_hwmod_sysc_type2,
1760 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1762 .sysc = &dra7xx_timer_1ms_sysc,
1765 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1767 .sysc_offs = 0x0010,
1768 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1769 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1770 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1772 .sysc_fields = &omap_hwmod_sysc_type2,
1775 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1777 .sysc = &dra7xx_timer_secure_sysc,
1780 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1782 .sysc_offs = 0x0010,
1783 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1784 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1785 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1787 .sysc_fields = &omap_hwmod_sysc_type2,
1790 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1792 .sysc = &dra7xx_timer_sysc,
1796 static struct omap_hwmod dra7xx_timer1_hwmod = {
1798 .class = &dra7xx_timer_1ms_hwmod_class,
1799 .clkdm_name = "wkupaon_clkdm",
1800 .main_clk = "timer1_gfclk_mux",
1803 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1804 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1805 .modulemode = MODULEMODE_SWCTRL,
1811 static struct omap_hwmod dra7xx_timer2_hwmod = {
1813 .class = &dra7xx_timer_1ms_hwmod_class,
1814 .clkdm_name = "l4per_clkdm",
1815 .main_clk = "timer2_gfclk_mux",
1818 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1819 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1820 .modulemode = MODULEMODE_SWCTRL,
1826 static struct omap_hwmod dra7xx_timer3_hwmod = {
1828 .class = &dra7xx_timer_hwmod_class,
1829 .clkdm_name = "l4per_clkdm",
1830 .main_clk = "timer3_gfclk_mux",
1833 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1834 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1835 .modulemode = MODULEMODE_SWCTRL,
1841 static struct omap_hwmod dra7xx_timer4_hwmod = {
1843 .class = &dra7xx_timer_secure_hwmod_class,
1844 .clkdm_name = "l4per_clkdm",
1845 .main_clk = "timer4_gfclk_mux",
1848 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1849 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1850 .modulemode = MODULEMODE_SWCTRL,
1856 static struct omap_hwmod dra7xx_timer5_hwmod = {
1858 .class = &dra7xx_timer_hwmod_class,
1859 .clkdm_name = "ipu_clkdm",
1860 .main_clk = "timer5_gfclk_mux",
1863 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1864 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1865 .modulemode = MODULEMODE_SWCTRL,
1871 static struct omap_hwmod dra7xx_timer6_hwmod = {
1873 .class = &dra7xx_timer_hwmod_class,
1874 .clkdm_name = "ipu_clkdm",
1875 .main_clk = "timer6_gfclk_mux",
1878 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1879 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1880 .modulemode = MODULEMODE_SWCTRL,
1886 static struct omap_hwmod dra7xx_timer7_hwmod = {
1888 .class = &dra7xx_timer_hwmod_class,
1889 .clkdm_name = "ipu_clkdm",
1890 .main_clk = "timer7_gfclk_mux",
1893 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1894 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1895 .modulemode = MODULEMODE_SWCTRL,
1901 static struct omap_hwmod dra7xx_timer8_hwmod = {
1903 .class = &dra7xx_timer_hwmod_class,
1904 .clkdm_name = "ipu_clkdm",
1905 .main_clk = "timer8_gfclk_mux",
1908 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1909 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1910 .modulemode = MODULEMODE_SWCTRL,
1916 static struct omap_hwmod dra7xx_timer9_hwmod = {
1918 .class = &dra7xx_timer_hwmod_class,
1919 .clkdm_name = "l4per_clkdm",
1920 .main_clk = "timer9_gfclk_mux",
1923 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1924 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1925 .modulemode = MODULEMODE_SWCTRL,
1931 static struct omap_hwmod dra7xx_timer10_hwmod = {
1933 .class = &dra7xx_timer_1ms_hwmod_class,
1934 .clkdm_name = "l4per_clkdm",
1935 .main_clk = "timer10_gfclk_mux",
1938 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1939 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1940 .modulemode = MODULEMODE_SWCTRL,
1946 static struct omap_hwmod dra7xx_timer11_hwmod = {
1948 .class = &dra7xx_timer_hwmod_class,
1949 .clkdm_name = "l4per_clkdm",
1950 .main_clk = "timer11_gfclk_mux",
1953 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1954 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1955 .modulemode = MODULEMODE_SWCTRL,
1965 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1967 .sysc_offs = 0x0054,
1968 .syss_offs = 0x0058,
1969 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1970 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1971 SYSS_HAS_RESET_STATUS),
1972 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1974 .sysc_fields = &omap_hwmod_sysc_type1,
1977 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1979 .sysc = &dra7xx_uart_sysc,
1983 static struct omap_hwmod dra7xx_uart1_hwmod = {
1985 .class = &dra7xx_uart_hwmod_class,
1986 .clkdm_name = "l4per_clkdm",
1987 .main_clk = "uart1_gfclk_mux",
1988 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
1991 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1992 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1993 .modulemode = MODULEMODE_SWCTRL,
1999 static struct omap_hwmod dra7xx_uart2_hwmod = {
2001 .class = &dra7xx_uart_hwmod_class,
2002 .clkdm_name = "l4per_clkdm",
2003 .main_clk = "uart2_gfclk_mux",
2004 .flags = HWMOD_SWSUP_SIDLE_ACT,
2007 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2008 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2009 .modulemode = MODULEMODE_SWCTRL,
2015 static struct omap_hwmod dra7xx_uart3_hwmod = {
2017 .class = &dra7xx_uart_hwmod_class,
2018 .clkdm_name = "l4per_clkdm",
2019 .main_clk = "uart3_gfclk_mux",
2020 .flags = HWMOD_SWSUP_SIDLE_ACT,
2023 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2024 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2025 .modulemode = MODULEMODE_SWCTRL,
2031 static struct omap_hwmod dra7xx_uart4_hwmod = {
2033 .class = &dra7xx_uart_hwmod_class,
2034 .clkdm_name = "l4per_clkdm",
2035 .main_clk = "uart4_gfclk_mux",
2036 .flags = HWMOD_SWSUP_SIDLE_ACT,
2039 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2040 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2041 .modulemode = MODULEMODE_SWCTRL,
2047 static struct omap_hwmod dra7xx_uart5_hwmod = {
2049 .class = &dra7xx_uart_hwmod_class,
2050 .clkdm_name = "l4per_clkdm",
2051 .main_clk = "uart5_gfclk_mux",
2052 .flags = HWMOD_SWSUP_SIDLE_ACT,
2055 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2056 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2057 .modulemode = MODULEMODE_SWCTRL,
2063 static struct omap_hwmod dra7xx_uart6_hwmod = {
2065 .class = &dra7xx_uart_hwmod_class,
2066 .clkdm_name = "ipu_clkdm",
2067 .main_clk = "uart6_gfclk_mux",
2068 .flags = HWMOD_SWSUP_SIDLE_ACT,
2071 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2072 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2073 .modulemode = MODULEMODE_SWCTRL,
2079 * 'usb_otg_ss' class
2083 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2085 .sysc_offs = 0x0010,
2086 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2087 SYSC_HAS_SIDLEMODE),
2088 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2089 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2090 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2091 .sysc_fields = &omap_hwmod_sysc_type2,
2094 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2095 .name = "usb_otg_ss",
2096 .sysc = &dra7xx_usb_otg_ss_sysc,
2100 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2101 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2104 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2105 .name = "usb_otg_ss1",
2106 .class = &dra7xx_usb_otg_ss_hwmod_class,
2107 .clkdm_name = "l3init_clkdm",
2108 .main_clk = "dpll_core_h13x2_ck",
2111 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2112 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2113 .modulemode = MODULEMODE_HWCTRL,
2116 .opt_clks = usb_otg_ss1_opt_clks,
2117 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2121 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2122 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2125 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2126 .name = "usb_otg_ss2",
2127 .class = &dra7xx_usb_otg_ss_hwmod_class,
2128 .clkdm_name = "l3init_clkdm",
2129 .main_clk = "dpll_core_h13x2_ck",
2132 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2133 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2134 .modulemode = MODULEMODE_HWCTRL,
2137 .opt_clks = usb_otg_ss2_opt_clks,
2138 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2142 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2143 .name = "usb_otg_ss3",
2144 .class = &dra7xx_usb_otg_ss_hwmod_class,
2145 .clkdm_name = "l3init_clkdm",
2146 .main_clk = "dpll_core_h13x2_ck",
2149 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2150 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2151 .modulemode = MODULEMODE_HWCTRL,
2157 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2158 .name = "usb_otg_ss4",
2159 .class = &dra7xx_usb_otg_ss_hwmod_class,
2160 .clkdm_name = "l3init_clkdm",
2161 .main_clk = "dpll_core_h13x2_ck",
2164 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2165 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2166 .modulemode = MODULEMODE_HWCTRL,
2176 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2181 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2183 .class = &dra7xx_vcp_hwmod_class,
2184 .clkdm_name = "l3main1_clkdm",
2185 .main_clk = "l3_iclk_div",
2188 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2189 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2195 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2197 .class = &dra7xx_vcp_hwmod_class,
2198 .clkdm_name = "l3main1_clkdm",
2199 .main_clk = "l3_iclk_div",
2202 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2203 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2213 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2215 .sysc_offs = 0x0010,
2216 .syss_offs = 0x0014,
2217 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2218 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2219 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2221 .sysc_fields = &omap_hwmod_sysc_type1,
2224 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2226 .sysc = &dra7xx_wd_timer_sysc,
2227 .pre_shutdown = &omap2_wd_timer_disable,
2228 .reset = &omap2_wd_timer_reset,
2232 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2233 .name = "wd_timer2",
2234 .class = &dra7xx_wd_timer_hwmod_class,
2235 .clkdm_name = "wkupaon_clkdm",
2236 .main_clk = "sys_32k_ck",
2239 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2240 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2241 .modulemode = MODULEMODE_SWCTRL,
2251 /* l3_main_2 -> l3_instr */
2252 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2253 .master = &dra7xx_l3_main_2_hwmod,
2254 .slave = &dra7xx_l3_instr_hwmod,
2255 .clk = "l3_iclk_div",
2256 .user = OCP_USER_MPU | OCP_USER_SDMA,
2259 /* l4_cfg -> l3_main_1 */
2260 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2261 .master = &dra7xx_l4_cfg_hwmod,
2262 .slave = &dra7xx_l3_main_1_hwmod,
2263 .clk = "l3_iclk_div",
2264 .user = OCP_USER_MPU | OCP_USER_SDMA,
2267 /* mpu -> l3_main_1 */
2268 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2269 .master = &dra7xx_mpu_hwmod,
2270 .slave = &dra7xx_l3_main_1_hwmod,
2271 .clk = "l3_iclk_div",
2272 .user = OCP_USER_MPU,
2275 /* l3_main_1 -> l3_main_2 */
2276 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2277 .master = &dra7xx_l3_main_1_hwmod,
2278 .slave = &dra7xx_l3_main_2_hwmod,
2279 .clk = "l3_iclk_div",
2280 .user = OCP_USER_MPU,
2283 /* l4_cfg -> l3_main_2 */
2284 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2285 .master = &dra7xx_l4_cfg_hwmod,
2286 .slave = &dra7xx_l3_main_2_hwmod,
2287 .clk = "l3_iclk_div",
2288 .user = OCP_USER_MPU | OCP_USER_SDMA,
2291 /* l3_main_1 -> l4_cfg */
2292 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2293 .master = &dra7xx_l3_main_1_hwmod,
2294 .slave = &dra7xx_l4_cfg_hwmod,
2295 .clk = "l3_iclk_div",
2296 .user = OCP_USER_MPU | OCP_USER_SDMA,
2299 /* l3_main_1 -> l4_per1 */
2300 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2301 .master = &dra7xx_l3_main_1_hwmod,
2302 .slave = &dra7xx_l4_per1_hwmod,
2303 .clk = "l3_iclk_div",
2304 .user = OCP_USER_MPU | OCP_USER_SDMA,
2307 /* l3_main_1 -> l4_per2 */
2308 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2309 .master = &dra7xx_l3_main_1_hwmod,
2310 .slave = &dra7xx_l4_per2_hwmod,
2311 .clk = "l3_iclk_div",
2312 .user = OCP_USER_MPU | OCP_USER_SDMA,
2315 /* l3_main_1 -> l4_per3 */
2316 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2317 .master = &dra7xx_l3_main_1_hwmod,
2318 .slave = &dra7xx_l4_per3_hwmod,
2319 .clk = "l3_iclk_div",
2320 .user = OCP_USER_MPU | OCP_USER_SDMA,
2323 /* l3_main_1 -> l4_wkup */
2324 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2325 .master = &dra7xx_l3_main_1_hwmod,
2326 .slave = &dra7xx_l4_wkup_hwmod,
2327 .clk = "wkupaon_iclk_mux",
2328 .user = OCP_USER_MPU | OCP_USER_SDMA,
2331 /* l4_per2 -> atl */
2332 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2333 .master = &dra7xx_l4_per2_hwmod,
2334 .slave = &dra7xx_atl_hwmod,
2335 .clk = "l3_iclk_div",
2336 .user = OCP_USER_MPU | OCP_USER_SDMA,
2339 /* l3_main_1 -> bb2d */
2340 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2341 .master = &dra7xx_l3_main_1_hwmod,
2342 .slave = &dra7xx_bb2d_hwmod,
2343 .clk = "l3_iclk_div",
2344 .user = OCP_USER_MPU | OCP_USER_SDMA,
2347 /* l4_wkup -> counter_32k */
2348 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2349 .master = &dra7xx_l4_wkup_hwmod,
2350 .slave = &dra7xx_counter_32k_hwmod,
2351 .clk = "wkupaon_iclk_mux",
2352 .user = OCP_USER_MPU | OCP_USER_SDMA,
2355 /* l4_wkup -> ctrl_module_wkup */
2356 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2357 .master = &dra7xx_l4_wkup_hwmod,
2358 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2359 .clk = "wkupaon_iclk_mux",
2360 .user = OCP_USER_MPU | OCP_USER_SDMA,
2363 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2364 .master = &dra7xx_l4_per2_hwmod,
2365 .slave = &dra7xx_gmac_hwmod,
2366 .clk = "dpll_gmac_ck",
2367 .user = OCP_USER_MPU,
2370 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2371 .master = &dra7xx_gmac_hwmod,
2372 .slave = &dra7xx_mdio_hwmod,
2373 .user = OCP_USER_MPU,
2376 /* l4_wkup -> dcan1 */
2377 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2378 .master = &dra7xx_l4_wkup_hwmod,
2379 .slave = &dra7xx_dcan1_hwmod,
2380 .clk = "wkupaon_iclk_mux",
2381 .user = OCP_USER_MPU | OCP_USER_SDMA,
2384 /* l4_per2 -> dcan2 */
2385 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2386 .master = &dra7xx_l4_per2_hwmod,
2387 .slave = &dra7xx_dcan2_hwmod,
2388 .clk = "l3_iclk_div",
2389 .user = OCP_USER_MPU | OCP_USER_SDMA,
2392 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2394 .pa_start = 0x4a056000,
2395 .pa_end = 0x4a056fff,
2396 .flags = ADDR_TYPE_RT
2401 /* l4_cfg -> dma_system */
2402 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2403 .master = &dra7xx_l4_cfg_hwmod,
2404 .slave = &dra7xx_dma_system_hwmod,
2405 .clk = "l3_iclk_div",
2406 .addr = dra7xx_dma_system_addrs,
2407 .user = OCP_USER_MPU | OCP_USER_SDMA,
2410 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2413 .pa_start = 0x58000000,
2414 .pa_end = 0x5800007f,
2415 .flags = ADDR_TYPE_RT
2419 /* l3_main_1 -> dss */
2420 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2421 .master = &dra7xx_l3_main_1_hwmod,
2422 .slave = &dra7xx_dss_hwmod,
2423 .clk = "l3_iclk_div",
2424 .addr = dra7xx_dss_addrs,
2425 .user = OCP_USER_MPU | OCP_USER_SDMA,
2428 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2431 .pa_start = 0x58001000,
2432 .pa_end = 0x58001fff,
2433 .flags = ADDR_TYPE_RT
2437 /* l3_main_1 -> dispc */
2438 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2439 .master = &dra7xx_l3_main_1_hwmod,
2440 .slave = &dra7xx_dss_dispc_hwmod,
2441 .clk = "l3_iclk_div",
2442 .addr = dra7xx_dss_dispc_addrs,
2443 .user = OCP_USER_MPU | OCP_USER_SDMA,
2446 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2449 .pa_start = 0x58040000,
2450 .pa_end = 0x580400ff,
2451 .flags = ADDR_TYPE_RT
2456 /* l3_main_1 -> dispc */
2457 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2458 .master = &dra7xx_l3_main_1_hwmod,
2459 .slave = &dra7xx_dss_hdmi_hwmod,
2460 .clk = "l3_iclk_div",
2461 .addr = dra7xx_dss_hdmi_addrs,
2462 .user = OCP_USER_MPU | OCP_USER_SDMA,
2465 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2467 .pa_start = 0x48078000,
2468 .pa_end = 0x48078fff,
2469 .flags = ADDR_TYPE_RT
2474 /* l4_per1 -> elm */
2475 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2476 .master = &dra7xx_l4_per1_hwmod,
2477 .slave = &dra7xx_elm_hwmod,
2478 .clk = "l3_iclk_div",
2479 .addr = dra7xx_elm_addrs,
2480 .user = OCP_USER_MPU | OCP_USER_SDMA,
2483 /* l4_wkup -> gpio1 */
2484 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2485 .master = &dra7xx_l4_wkup_hwmod,
2486 .slave = &dra7xx_gpio1_hwmod,
2487 .clk = "wkupaon_iclk_mux",
2488 .user = OCP_USER_MPU | OCP_USER_SDMA,
2491 /* l4_per1 -> gpio2 */
2492 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2493 .master = &dra7xx_l4_per1_hwmod,
2494 .slave = &dra7xx_gpio2_hwmod,
2495 .clk = "l3_iclk_div",
2496 .user = OCP_USER_MPU | OCP_USER_SDMA,
2499 /* l4_per1 -> gpio3 */
2500 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2501 .master = &dra7xx_l4_per1_hwmod,
2502 .slave = &dra7xx_gpio3_hwmod,
2503 .clk = "l3_iclk_div",
2504 .user = OCP_USER_MPU | OCP_USER_SDMA,
2507 /* l4_per1 -> gpio4 */
2508 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2509 .master = &dra7xx_l4_per1_hwmod,
2510 .slave = &dra7xx_gpio4_hwmod,
2511 .clk = "l3_iclk_div",
2512 .user = OCP_USER_MPU | OCP_USER_SDMA,
2515 /* l4_per1 -> gpio5 */
2516 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2517 .master = &dra7xx_l4_per1_hwmod,
2518 .slave = &dra7xx_gpio5_hwmod,
2519 .clk = "l3_iclk_div",
2520 .user = OCP_USER_MPU | OCP_USER_SDMA,
2523 /* l4_per1 -> gpio6 */
2524 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2525 .master = &dra7xx_l4_per1_hwmod,
2526 .slave = &dra7xx_gpio6_hwmod,
2527 .clk = "l3_iclk_div",
2528 .user = OCP_USER_MPU | OCP_USER_SDMA,
2531 /* l4_per1 -> gpio7 */
2532 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2533 .master = &dra7xx_l4_per1_hwmod,
2534 .slave = &dra7xx_gpio7_hwmod,
2535 .clk = "l3_iclk_div",
2536 .user = OCP_USER_MPU | OCP_USER_SDMA,
2539 /* l4_per1 -> gpio8 */
2540 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2541 .master = &dra7xx_l4_per1_hwmod,
2542 .slave = &dra7xx_gpio8_hwmod,
2543 .clk = "l3_iclk_div",
2544 .user = OCP_USER_MPU | OCP_USER_SDMA,
2547 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2549 .pa_start = 0x50000000,
2550 .pa_end = 0x500003ff,
2551 .flags = ADDR_TYPE_RT
2556 /* l3_main_1 -> gpmc */
2557 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2558 .master = &dra7xx_l3_main_1_hwmod,
2559 .slave = &dra7xx_gpmc_hwmod,
2560 .clk = "l3_iclk_div",
2561 .addr = dra7xx_gpmc_addrs,
2562 .user = OCP_USER_MPU | OCP_USER_SDMA,
2565 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2567 .pa_start = 0x480b2000,
2568 .pa_end = 0x480b201f,
2569 .flags = ADDR_TYPE_RT
2574 /* l4_per1 -> hdq1w */
2575 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2576 .master = &dra7xx_l4_per1_hwmod,
2577 .slave = &dra7xx_hdq1w_hwmod,
2578 .clk = "l3_iclk_div",
2579 .addr = dra7xx_hdq1w_addrs,
2580 .user = OCP_USER_MPU | OCP_USER_SDMA,
2583 /* l4_per1 -> i2c1 */
2584 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2585 .master = &dra7xx_l4_per1_hwmod,
2586 .slave = &dra7xx_i2c1_hwmod,
2587 .clk = "l3_iclk_div",
2588 .user = OCP_USER_MPU | OCP_USER_SDMA,
2591 /* l4_per1 -> i2c2 */
2592 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2593 .master = &dra7xx_l4_per1_hwmod,
2594 .slave = &dra7xx_i2c2_hwmod,
2595 .clk = "l3_iclk_div",
2596 .user = OCP_USER_MPU | OCP_USER_SDMA,
2599 /* l4_per1 -> i2c3 */
2600 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2601 .master = &dra7xx_l4_per1_hwmod,
2602 .slave = &dra7xx_i2c3_hwmod,
2603 .clk = "l3_iclk_div",
2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
2607 /* l4_per1 -> i2c4 */
2608 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2609 .master = &dra7xx_l4_per1_hwmod,
2610 .slave = &dra7xx_i2c4_hwmod,
2611 .clk = "l3_iclk_div",
2612 .user = OCP_USER_MPU | OCP_USER_SDMA,
2615 /* l4_per1 -> i2c5 */
2616 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2617 .master = &dra7xx_l4_per1_hwmod,
2618 .slave = &dra7xx_i2c5_hwmod,
2619 .clk = "l3_iclk_div",
2620 .user = OCP_USER_MPU | OCP_USER_SDMA,
2623 /* l4_cfg -> mailbox1 */
2624 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2625 .master = &dra7xx_l4_cfg_hwmod,
2626 .slave = &dra7xx_mailbox1_hwmod,
2627 .clk = "l3_iclk_div",
2628 .user = OCP_USER_MPU | OCP_USER_SDMA,
2631 /* l4_per3 -> mailbox2 */
2632 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2633 .master = &dra7xx_l4_per3_hwmod,
2634 .slave = &dra7xx_mailbox2_hwmod,
2635 .clk = "l3_iclk_div",
2636 .user = OCP_USER_MPU | OCP_USER_SDMA,
2639 /* l4_per3 -> mailbox3 */
2640 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2641 .master = &dra7xx_l4_per3_hwmod,
2642 .slave = &dra7xx_mailbox3_hwmod,
2643 .clk = "l3_iclk_div",
2644 .user = OCP_USER_MPU | OCP_USER_SDMA,
2647 /* l4_per3 -> mailbox4 */
2648 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2649 .master = &dra7xx_l4_per3_hwmod,
2650 .slave = &dra7xx_mailbox4_hwmod,
2651 .clk = "l3_iclk_div",
2652 .user = OCP_USER_MPU | OCP_USER_SDMA,
2655 /* l4_per3 -> mailbox5 */
2656 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2657 .master = &dra7xx_l4_per3_hwmod,
2658 .slave = &dra7xx_mailbox5_hwmod,
2659 .clk = "l3_iclk_div",
2660 .user = OCP_USER_MPU | OCP_USER_SDMA,
2663 /* l4_per3 -> mailbox6 */
2664 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2665 .master = &dra7xx_l4_per3_hwmod,
2666 .slave = &dra7xx_mailbox6_hwmod,
2667 .clk = "l3_iclk_div",
2668 .user = OCP_USER_MPU | OCP_USER_SDMA,
2671 /* l4_per3 -> mailbox7 */
2672 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2673 .master = &dra7xx_l4_per3_hwmod,
2674 .slave = &dra7xx_mailbox7_hwmod,
2675 .clk = "l3_iclk_div",
2676 .user = OCP_USER_MPU | OCP_USER_SDMA,
2679 /* l4_per3 -> mailbox8 */
2680 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2681 .master = &dra7xx_l4_per3_hwmod,
2682 .slave = &dra7xx_mailbox8_hwmod,
2683 .clk = "l3_iclk_div",
2684 .user = OCP_USER_MPU | OCP_USER_SDMA,
2687 /* l4_per3 -> mailbox9 */
2688 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2689 .master = &dra7xx_l4_per3_hwmod,
2690 .slave = &dra7xx_mailbox9_hwmod,
2691 .clk = "l3_iclk_div",
2692 .user = OCP_USER_MPU | OCP_USER_SDMA,
2695 /* l4_per3 -> mailbox10 */
2696 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2697 .master = &dra7xx_l4_per3_hwmod,
2698 .slave = &dra7xx_mailbox10_hwmod,
2699 .clk = "l3_iclk_div",
2700 .user = OCP_USER_MPU | OCP_USER_SDMA,
2703 /* l4_per3 -> mailbox11 */
2704 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2705 .master = &dra7xx_l4_per3_hwmod,
2706 .slave = &dra7xx_mailbox11_hwmod,
2707 .clk = "l3_iclk_div",
2708 .user = OCP_USER_MPU | OCP_USER_SDMA,
2711 /* l4_per3 -> mailbox12 */
2712 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2713 .master = &dra7xx_l4_per3_hwmod,
2714 .slave = &dra7xx_mailbox12_hwmod,
2715 .clk = "l3_iclk_div",
2716 .user = OCP_USER_MPU | OCP_USER_SDMA,
2719 /* l4_per3 -> mailbox13 */
2720 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2721 .master = &dra7xx_l4_per3_hwmod,
2722 .slave = &dra7xx_mailbox13_hwmod,
2723 .clk = "l3_iclk_div",
2724 .user = OCP_USER_MPU | OCP_USER_SDMA,
2727 /* l4_per1 -> mcspi1 */
2728 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2729 .master = &dra7xx_l4_per1_hwmod,
2730 .slave = &dra7xx_mcspi1_hwmod,
2731 .clk = "l3_iclk_div",
2732 .user = OCP_USER_MPU | OCP_USER_SDMA,
2735 /* l4_per1 -> mcspi2 */
2736 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2737 .master = &dra7xx_l4_per1_hwmod,
2738 .slave = &dra7xx_mcspi2_hwmod,
2739 .clk = "l3_iclk_div",
2740 .user = OCP_USER_MPU | OCP_USER_SDMA,
2743 /* l4_per1 -> mcspi3 */
2744 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2745 .master = &dra7xx_l4_per1_hwmod,
2746 .slave = &dra7xx_mcspi3_hwmod,
2747 .clk = "l3_iclk_div",
2748 .user = OCP_USER_MPU | OCP_USER_SDMA,
2751 /* l4_per1 -> mcspi4 */
2752 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2753 .master = &dra7xx_l4_per1_hwmod,
2754 .slave = &dra7xx_mcspi4_hwmod,
2755 .clk = "l3_iclk_div",
2756 .user = OCP_USER_MPU | OCP_USER_SDMA,
2759 /* l4_per1 -> mmc1 */
2760 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2761 .master = &dra7xx_l4_per1_hwmod,
2762 .slave = &dra7xx_mmc1_hwmod,
2763 .clk = "l3_iclk_div",
2764 .user = OCP_USER_MPU | OCP_USER_SDMA,
2767 /* l4_per1 -> mmc2 */
2768 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2769 .master = &dra7xx_l4_per1_hwmod,
2770 .slave = &dra7xx_mmc2_hwmod,
2771 .clk = "l3_iclk_div",
2772 .user = OCP_USER_MPU | OCP_USER_SDMA,
2775 /* l4_per1 -> mmc3 */
2776 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2777 .master = &dra7xx_l4_per1_hwmod,
2778 .slave = &dra7xx_mmc3_hwmod,
2779 .clk = "l3_iclk_div",
2780 .user = OCP_USER_MPU | OCP_USER_SDMA,
2783 /* l4_per1 -> mmc4 */
2784 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2785 .master = &dra7xx_l4_per1_hwmod,
2786 .slave = &dra7xx_mmc4_hwmod,
2787 .clk = "l3_iclk_div",
2788 .user = OCP_USER_MPU | OCP_USER_SDMA,
2792 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2793 .master = &dra7xx_l4_cfg_hwmod,
2794 .slave = &dra7xx_mpu_hwmod,
2795 .clk = "l3_iclk_div",
2796 .user = OCP_USER_MPU | OCP_USER_SDMA,
2799 /* l4_cfg -> ocp2scp1 */
2800 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2801 .master = &dra7xx_l4_cfg_hwmod,
2802 .slave = &dra7xx_ocp2scp1_hwmod,
2803 .clk = "l4_root_clk_div",
2804 .user = OCP_USER_MPU | OCP_USER_SDMA,
2807 /* l4_cfg -> ocp2scp3 */
2808 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2809 .master = &dra7xx_l4_cfg_hwmod,
2810 .slave = &dra7xx_ocp2scp3_hwmod,
2811 .clk = "l4_root_clk_div",
2812 .user = OCP_USER_MPU | OCP_USER_SDMA,
2815 /* l3_main_1 -> pcie1 */
2816 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
2817 .master = &dra7xx_l3_main_1_hwmod,
2818 .slave = &dra7xx_pcie1_hwmod,
2819 .clk = "l3_iclk_div",
2820 .user = OCP_USER_MPU | OCP_USER_SDMA,
2823 /* l4_cfg -> pcie1 */
2824 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
2825 .master = &dra7xx_l4_cfg_hwmod,
2826 .slave = &dra7xx_pcie1_hwmod,
2827 .clk = "l4_root_clk_div",
2828 .user = OCP_USER_MPU | OCP_USER_SDMA,
2831 /* l3_main_1 -> pcie2 */
2832 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
2833 .master = &dra7xx_l3_main_1_hwmod,
2834 .slave = &dra7xx_pcie2_hwmod,
2835 .clk = "l3_iclk_div",
2836 .user = OCP_USER_MPU | OCP_USER_SDMA,
2839 /* l4_cfg -> pcie2 */
2840 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
2841 .master = &dra7xx_l4_cfg_hwmod,
2842 .slave = &dra7xx_pcie2_hwmod,
2843 .clk = "l4_root_clk_div",
2844 .user = OCP_USER_MPU | OCP_USER_SDMA,
2847 /* l4_cfg -> pcie1 phy */
2848 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
2849 .master = &dra7xx_l4_cfg_hwmod,
2850 .slave = &dra7xx_pcie1_phy_hwmod,
2851 .clk = "l4_root_clk_div",
2852 .user = OCP_USER_MPU | OCP_USER_SDMA,
2855 /* l4_cfg -> pcie2 phy */
2856 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
2857 .master = &dra7xx_l4_cfg_hwmod,
2858 .slave = &dra7xx_pcie2_phy_hwmod,
2859 .clk = "l4_root_clk_div",
2860 .user = OCP_USER_MPU | OCP_USER_SDMA,
2863 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2865 .pa_start = 0x4b300000,
2866 .pa_end = 0x4b30007f,
2867 .flags = ADDR_TYPE_RT
2872 /* l3_main_1 -> qspi */
2873 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2874 .master = &dra7xx_l3_main_1_hwmod,
2875 .slave = &dra7xx_qspi_hwmod,
2876 .clk = "l3_iclk_div",
2877 .addr = dra7xx_qspi_addrs,
2878 .user = OCP_USER_MPU | OCP_USER_SDMA,
2881 /* l4_per3 -> rtcss */
2882 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2883 .master = &dra7xx_l4_per3_hwmod,
2884 .slave = &dra7xx_rtcss_hwmod,
2885 .clk = "l4_root_clk_div",
2886 .user = OCP_USER_MPU | OCP_USER_SDMA,
2889 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2892 .pa_start = 0x4a141100,
2893 .pa_end = 0x4a141107,
2894 .flags = ADDR_TYPE_RT
2899 /* l4_cfg -> sata */
2900 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2901 .master = &dra7xx_l4_cfg_hwmod,
2902 .slave = &dra7xx_sata_hwmod,
2903 .clk = "l3_iclk_div",
2904 .addr = dra7xx_sata_addrs,
2905 .user = OCP_USER_MPU | OCP_USER_SDMA,
2908 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2910 .pa_start = 0x4a0dd000,
2911 .pa_end = 0x4a0dd07f,
2912 .flags = ADDR_TYPE_RT
2917 /* l4_cfg -> smartreflex_core */
2918 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2919 .master = &dra7xx_l4_cfg_hwmod,
2920 .slave = &dra7xx_smartreflex_core_hwmod,
2921 .clk = "l4_root_clk_div",
2922 .addr = dra7xx_smartreflex_core_addrs,
2923 .user = OCP_USER_MPU | OCP_USER_SDMA,
2926 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2928 .pa_start = 0x4a0d9000,
2929 .pa_end = 0x4a0d907f,
2930 .flags = ADDR_TYPE_RT
2935 /* l4_cfg -> smartreflex_mpu */
2936 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2937 .master = &dra7xx_l4_cfg_hwmod,
2938 .slave = &dra7xx_smartreflex_mpu_hwmod,
2939 .clk = "l4_root_clk_div",
2940 .addr = dra7xx_smartreflex_mpu_addrs,
2941 .user = OCP_USER_MPU | OCP_USER_SDMA,
2944 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2946 .pa_start = 0x4a0f6000,
2947 .pa_end = 0x4a0f6fff,
2948 .flags = ADDR_TYPE_RT
2953 /* l4_cfg -> spinlock */
2954 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2955 .master = &dra7xx_l4_cfg_hwmod,
2956 .slave = &dra7xx_spinlock_hwmod,
2957 .clk = "l3_iclk_div",
2958 .addr = dra7xx_spinlock_addrs,
2959 .user = OCP_USER_MPU | OCP_USER_SDMA,
2962 /* l4_wkup -> timer1 */
2963 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2964 .master = &dra7xx_l4_wkup_hwmod,
2965 .slave = &dra7xx_timer1_hwmod,
2966 .clk = "wkupaon_iclk_mux",
2967 .user = OCP_USER_MPU | OCP_USER_SDMA,
2970 /* l4_per1 -> timer2 */
2971 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2972 .master = &dra7xx_l4_per1_hwmod,
2973 .slave = &dra7xx_timer2_hwmod,
2974 .clk = "l3_iclk_div",
2975 .user = OCP_USER_MPU | OCP_USER_SDMA,
2978 /* l4_per1 -> timer3 */
2979 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2980 .master = &dra7xx_l4_per1_hwmod,
2981 .slave = &dra7xx_timer3_hwmod,
2982 .clk = "l3_iclk_div",
2983 .user = OCP_USER_MPU | OCP_USER_SDMA,
2986 /* l4_per1 -> timer4 */
2987 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2988 .master = &dra7xx_l4_per1_hwmod,
2989 .slave = &dra7xx_timer4_hwmod,
2990 .clk = "l3_iclk_div",
2991 .user = OCP_USER_MPU | OCP_USER_SDMA,
2994 /* l4_per3 -> timer5 */
2995 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2996 .master = &dra7xx_l4_per3_hwmod,
2997 .slave = &dra7xx_timer5_hwmod,
2998 .clk = "l3_iclk_div",
2999 .user = OCP_USER_MPU | OCP_USER_SDMA,
3002 /* l4_per3 -> timer6 */
3003 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3004 .master = &dra7xx_l4_per3_hwmod,
3005 .slave = &dra7xx_timer6_hwmod,
3006 .clk = "l3_iclk_div",
3007 .user = OCP_USER_MPU | OCP_USER_SDMA,
3010 /* l4_per3 -> timer7 */
3011 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3012 .master = &dra7xx_l4_per3_hwmod,
3013 .slave = &dra7xx_timer7_hwmod,
3014 .clk = "l3_iclk_div",
3015 .user = OCP_USER_MPU | OCP_USER_SDMA,
3018 /* l4_per3 -> timer8 */
3019 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3020 .master = &dra7xx_l4_per3_hwmod,
3021 .slave = &dra7xx_timer8_hwmod,
3022 .clk = "l3_iclk_div",
3023 .user = OCP_USER_MPU | OCP_USER_SDMA,
3026 /* l4_per1 -> timer9 */
3027 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3028 .master = &dra7xx_l4_per1_hwmod,
3029 .slave = &dra7xx_timer9_hwmod,
3030 .clk = "l3_iclk_div",
3031 .user = OCP_USER_MPU | OCP_USER_SDMA,
3034 /* l4_per1 -> timer10 */
3035 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3036 .master = &dra7xx_l4_per1_hwmod,
3037 .slave = &dra7xx_timer10_hwmod,
3038 .clk = "l3_iclk_div",
3039 .user = OCP_USER_MPU | OCP_USER_SDMA,
3042 /* l4_per1 -> timer11 */
3043 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3044 .master = &dra7xx_l4_per1_hwmod,
3045 .slave = &dra7xx_timer11_hwmod,
3046 .clk = "l3_iclk_div",
3047 .user = OCP_USER_MPU | OCP_USER_SDMA,
3050 /* l4_per1 -> uart1 */
3051 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3052 .master = &dra7xx_l4_per1_hwmod,
3053 .slave = &dra7xx_uart1_hwmod,
3054 .clk = "l3_iclk_div",
3055 .user = OCP_USER_MPU | OCP_USER_SDMA,
3058 /* l4_per1 -> uart2 */
3059 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3060 .master = &dra7xx_l4_per1_hwmod,
3061 .slave = &dra7xx_uart2_hwmod,
3062 .clk = "l3_iclk_div",
3063 .user = OCP_USER_MPU | OCP_USER_SDMA,
3066 /* l4_per1 -> uart3 */
3067 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3068 .master = &dra7xx_l4_per1_hwmod,
3069 .slave = &dra7xx_uart3_hwmod,
3070 .clk = "l3_iclk_div",
3071 .user = OCP_USER_MPU | OCP_USER_SDMA,
3074 /* l4_per1 -> uart4 */
3075 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3076 .master = &dra7xx_l4_per1_hwmod,
3077 .slave = &dra7xx_uart4_hwmod,
3078 .clk = "l3_iclk_div",
3079 .user = OCP_USER_MPU | OCP_USER_SDMA,
3082 /* l4_per1 -> uart5 */
3083 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3084 .master = &dra7xx_l4_per1_hwmod,
3085 .slave = &dra7xx_uart5_hwmod,
3086 .clk = "l3_iclk_div",
3087 .user = OCP_USER_MPU | OCP_USER_SDMA,
3090 /* l4_per1 -> uart6 */
3091 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3092 .master = &dra7xx_l4_per1_hwmod,
3093 .slave = &dra7xx_uart6_hwmod,
3094 .clk = "l3_iclk_div",
3095 .user = OCP_USER_MPU | OCP_USER_SDMA,
3098 /* l4_per3 -> usb_otg_ss1 */
3099 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3100 .master = &dra7xx_l4_per3_hwmod,
3101 .slave = &dra7xx_usb_otg_ss1_hwmod,
3102 .clk = "dpll_core_h13x2_ck",
3103 .user = OCP_USER_MPU | OCP_USER_SDMA,
3106 /* l4_per3 -> usb_otg_ss2 */
3107 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3108 .master = &dra7xx_l4_per3_hwmod,
3109 .slave = &dra7xx_usb_otg_ss2_hwmod,
3110 .clk = "dpll_core_h13x2_ck",
3111 .user = OCP_USER_MPU | OCP_USER_SDMA,
3114 /* l4_per3 -> usb_otg_ss3 */
3115 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3116 .master = &dra7xx_l4_per3_hwmod,
3117 .slave = &dra7xx_usb_otg_ss3_hwmod,
3118 .clk = "dpll_core_h13x2_ck",
3119 .user = OCP_USER_MPU | OCP_USER_SDMA,
3122 /* l4_per3 -> usb_otg_ss4 */
3123 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3124 .master = &dra7xx_l4_per3_hwmod,
3125 .slave = &dra7xx_usb_otg_ss4_hwmod,
3126 .clk = "dpll_core_h13x2_ck",
3127 .user = OCP_USER_MPU | OCP_USER_SDMA,
3130 /* l3_main_1 -> vcp1 */
3131 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3132 .master = &dra7xx_l3_main_1_hwmod,
3133 .slave = &dra7xx_vcp1_hwmod,
3134 .clk = "l3_iclk_div",
3135 .user = OCP_USER_MPU | OCP_USER_SDMA,
3138 /* l4_per2 -> vcp1 */
3139 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3140 .master = &dra7xx_l4_per2_hwmod,
3141 .slave = &dra7xx_vcp1_hwmod,
3142 .clk = "l3_iclk_div",
3143 .user = OCP_USER_MPU | OCP_USER_SDMA,
3146 /* l3_main_1 -> vcp2 */
3147 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3148 .master = &dra7xx_l3_main_1_hwmod,
3149 .slave = &dra7xx_vcp2_hwmod,
3150 .clk = "l3_iclk_div",
3151 .user = OCP_USER_MPU | OCP_USER_SDMA,
3154 /* l4_per2 -> vcp2 */
3155 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3156 .master = &dra7xx_l4_per2_hwmod,
3157 .slave = &dra7xx_vcp2_hwmod,
3158 .clk = "l3_iclk_div",
3159 .user = OCP_USER_MPU | OCP_USER_SDMA,
3162 /* l4_wkup -> wd_timer2 */
3163 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3164 .master = &dra7xx_l4_wkup_hwmod,
3165 .slave = &dra7xx_wd_timer2_hwmod,
3166 .clk = "wkupaon_iclk_mux",
3167 .user = OCP_USER_MPU | OCP_USER_SDMA,
3170 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3171 &dra7xx_l3_main_2__l3_instr,
3172 &dra7xx_l4_cfg__l3_main_1,
3173 &dra7xx_mpu__l3_main_1,
3174 &dra7xx_l3_main_1__l3_main_2,
3175 &dra7xx_l4_cfg__l3_main_2,
3176 &dra7xx_l3_main_1__l4_cfg,
3177 &dra7xx_l3_main_1__l4_per1,
3178 &dra7xx_l3_main_1__l4_per2,
3179 &dra7xx_l3_main_1__l4_per3,
3180 &dra7xx_l3_main_1__l4_wkup,
3181 &dra7xx_l4_per2__atl,
3182 &dra7xx_l3_main_1__bb2d,
3183 &dra7xx_l4_wkup__counter_32k,
3184 &dra7xx_l4_wkup__ctrl_module_wkup,
3185 &dra7xx_l4_wkup__dcan1,
3186 &dra7xx_l4_per2__dcan2,
3187 &dra7xx_l4_per2__cpgmac0,
3189 &dra7xx_l4_cfg__dma_system,
3190 &dra7xx_l3_main_1__dss,
3191 &dra7xx_l3_main_1__dispc,
3192 &dra7xx_l3_main_1__hdmi,
3193 &dra7xx_l4_per1__elm,
3194 &dra7xx_l4_wkup__gpio1,
3195 &dra7xx_l4_per1__gpio2,
3196 &dra7xx_l4_per1__gpio3,
3197 &dra7xx_l4_per1__gpio4,
3198 &dra7xx_l4_per1__gpio5,
3199 &dra7xx_l4_per1__gpio6,
3200 &dra7xx_l4_per1__gpio7,
3201 &dra7xx_l4_per1__gpio8,
3202 &dra7xx_l3_main_1__gpmc,
3203 &dra7xx_l4_per1__hdq1w,
3204 &dra7xx_l4_per1__i2c1,
3205 &dra7xx_l4_per1__i2c2,
3206 &dra7xx_l4_per1__i2c3,
3207 &dra7xx_l4_per1__i2c4,
3208 &dra7xx_l4_per1__i2c5,
3209 &dra7xx_l4_cfg__mailbox1,
3210 &dra7xx_l4_per3__mailbox2,
3211 &dra7xx_l4_per3__mailbox3,
3212 &dra7xx_l4_per3__mailbox4,
3213 &dra7xx_l4_per3__mailbox5,
3214 &dra7xx_l4_per3__mailbox6,
3215 &dra7xx_l4_per3__mailbox7,
3216 &dra7xx_l4_per3__mailbox8,
3217 &dra7xx_l4_per3__mailbox9,
3218 &dra7xx_l4_per3__mailbox10,
3219 &dra7xx_l4_per3__mailbox11,
3220 &dra7xx_l4_per3__mailbox12,
3221 &dra7xx_l4_per3__mailbox13,
3222 &dra7xx_l4_per1__mcspi1,
3223 &dra7xx_l4_per1__mcspi2,
3224 &dra7xx_l4_per1__mcspi3,
3225 &dra7xx_l4_per1__mcspi4,
3226 &dra7xx_l4_per1__mmc1,
3227 &dra7xx_l4_per1__mmc2,
3228 &dra7xx_l4_per1__mmc3,
3229 &dra7xx_l4_per1__mmc4,
3230 &dra7xx_l4_cfg__mpu,
3231 &dra7xx_l4_cfg__ocp2scp1,
3232 &dra7xx_l4_cfg__ocp2scp3,
3233 &dra7xx_l3_main_1__pcie1,
3234 &dra7xx_l4_cfg__pcie1,
3235 &dra7xx_l3_main_1__pcie2,
3236 &dra7xx_l4_cfg__pcie2,
3237 &dra7xx_l4_cfg__pcie1_phy,
3238 &dra7xx_l4_cfg__pcie2_phy,
3239 &dra7xx_l3_main_1__qspi,
3240 &dra7xx_l4_per3__rtcss,
3241 &dra7xx_l4_cfg__sata,
3242 &dra7xx_l4_cfg__smartreflex_core,
3243 &dra7xx_l4_cfg__smartreflex_mpu,
3244 &dra7xx_l4_cfg__spinlock,
3245 &dra7xx_l4_wkup__timer1,
3246 &dra7xx_l4_per1__timer2,
3247 &dra7xx_l4_per1__timer3,
3248 &dra7xx_l4_per1__timer4,
3249 &dra7xx_l4_per3__timer5,
3250 &dra7xx_l4_per3__timer6,
3251 &dra7xx_l4_per3__timer7,
3252 &dra7xx_l4_per3__timer8,
3253 &dra7xx_l4_per1__timer9,
3254 &dra7xx_l4_per1__timer10,
3255 &dra7xx_l4_per1__timer11,
3256 &dra7xx_l4_per1__uart1,
3257 &dra7xx_l4_per1__uart2,
3258 &dra7xx_l4_per1__uart3,
3259 &dra7xx_l4_per1__uart4,
3260 &dra7xx_l4_per1__uart5,
3261 &dra7xx_l4_per1__uart6,
3262 &dra7xx_l4_per3__usb_otg_ss1,
3263 &dra7xx_l4_per3__usb_otg_ss2,
3264 &dra7xx_l4_per3__usb_otg_ss3,
3265 &dra7xx_l3_main_1__vcp1,
3266 &dra7xx_l4_per2__vcp1,
3267 &dra7xx_l3_main_1__vcp2,
3268 &dra7xx_l4_per2__vcp2,
3269 &dra7xx_l4_wkup__wd_timer2,
3273 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3274 &dra7xx_l4_per3__usb_otg_ss4,
3278 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3282 int __init dra7xx_hwmod_init(void)
3287 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3289 if (!ret && soc_is_dra74x())
3290 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3291 else if (!ret && soc_is_dra72x())
3292 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);