Merge patch series "riscv: Add remaining module relocations and tests"

Charlie Jenkins <charlie@rivosinc.com> says:

A handful of module relocations were missing, this patch includes the
remaining ones. I also wrote some test cases to ensure that module
loading works properly. Some relocations cannot be supported in the
kernel, these include the ones that rely on thread local storage and
dynamic linking.

This patch also overhauls the implementation of ADD/SUB/SET/ULEB128
relocations to handle overflow. "Overflow" is different for ULEB128
since it is a variable-length encoding that the compiler can be expected
to generate enough space for. Instead of overflowing, ULEB128 will
expand into the next 8-bit segment of the location.

A psABI proposal [1] was merged that mandates that SET_ULEB128 and
SUB_ULEB128 are paired, however the discussion following the merging of
the pull request revealed that while the pull request was valid, it
would be better for linkers to properly handle this overflow. This patch
proactively implements this methodology for future compatibility.

This can be tested by enabling KUNIT, RUNTIME_KERNEL_TESTING_MENU, and
RISCV_MODULE_LINKING_KUNIT.

[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/403

* b4-shazam-merge:
  riscv: Add tests for riscv module loading
  riscv: Add remaining module relocations
  riscv: Avoid unaligned access when relocating modules

Link: https://lore.kernel.org/r/20231101-module_relocations-v9-0-8dfa3483c400@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --cc arch/riscv/kernel/Makefile
index 0d874fb24b516191b7582110352587204dfdf551,bb99657252f41cdb5b59d4f15887de405b9bdaca..fee22a3d1b53462a33bad285d345465a0100e6a9
--- 1/arch/riscv/kernel/Makefile
--- 2/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@@ -57,9 -57,10 +57,10 @@@ obj-y       += stacktrace.
  obj-y += cacheinfo.o
  obj-y += patch.o
  obj-y += probes/
+ obj-y += tests/
  obj-$(CONFIG_MMU) += vdso.o vdso/
  
 -obj-$(CONFIG_RISCV_M_MODE)    += traps_misaligned.o
 +obj-$(CONFIG_RISCV_MISALIGNED)        += traps_misaligned.o
  obj-$(CONFIG_FPU)             += fpu.o
  obj-$(CONFIG_RISCV_ISA_V)     += vector.o
  obj-$(CONFIG_SMP)             += smpboot.o