1 // SPDX-License-Identifier: GPL-2.0-only
3 * Machine check handler.
5 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
6 * Rest from unknown author(s).
7 * 2004 Andi Kleen. Rewrote most of it.
8 * Copyright 2008 Intel Corporation
12 #include <linux/thread_info.h>
13 #include <linux/capability.h>
14 #include <linux/miscdevice.h>
15 #include <linux/ratelimit.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/device.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/delay.h>
26 #include <linux/ctype.h>
27 #include <linux/sched.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/kmod.h>
33 #include <linux/poll.h>
34 #include <linux/nmi.h>
35 #include <linux/cpu.h>
36 #include <linux/ras.h>
37 #include <linux/smp.h>
40 #include <linux/debugfs.h>
41 #include <linux/irq_work.h>
42 #include <linux/export.h>
43 #include <linux/set_memory.h>
44 #include <linux/sync_core.h>
45 #include <linux/task_work.h>
46 #include <linux/hardirq.h>
48 #include <asm/intel-family.h>
49 #include <asm/processor.h>
50 #include <asm/traps.h>
51 #include <asm/tlbflush.h>
54 #include <asm/reboot.h>
59 /* sysfs synchronization */
60 static DEFINE_MUTEX(mce_sysfs_mutex);
62 #define CREATE_TRACE_POINTS
63 #include <trace/events/mce.h>
65 #define SPINUNIT 100 /* 100ns */
67 DEFINE_PER_CPU(unsigned, mce_exception_count);
69 DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
71 DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
74 /* One object for each MCE bank, shared by all CPUs */
76 struct device_attribute attr; /* device attribute */
77 char attrname[ATTR_LEN]; /* attribute name */
78 u8 bank; /* bank number */
80 static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS];
82 struct mce_vendor_flags mce_flags __read_mostly;
84 struct mca_config mca_cfg __read_mostly = {
89 static DEFINE_PER_CPU(struct mce, mces_seen);
90 static unsigned long mce_need_notify;
93 * MCA banks polled by the period polling timer for corrected events.
94 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
96 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
97 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
101 * MCA banks controlled through firmware first for corrected errors.
102 * This is a global list of banks for which we won't enable CMCI and we
103 * won't poll. Firmware controls these banks and is responsible for
104 * reporting corrected errors through GHES. Uncorrected/recoverable
105 * errors are still notified through a machine check.
107 mce_banks_t mce_banks_ce_disabled;
109 static struct work_struct mce_work;
110 static struct irq_work mce_irq_work;
113 * CPU/chipset specific EDAC code can register a notifier call here to print
114 * MCE errors in a human-readable form.
116 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
118 /* Do initial initialization of a struct mce */
119 void mce_setup(struct mce *m)
121 memset(m, 0, sizeof(struct mce));
122 m->cpu = m->extcpu = smp_processor_id();
123 /* need the internal __ version to avoid deadlocks */
124 m->time = __ktime_get_real_seconds();
125 m->cpuvendor = boot_cpu_data.x86_vendor;
126 m->cpuid = cpuid_eax(1);
127 m->socketid = cpu_data(m->extcpu).topo.pkg_id;
128 m->apicid = cpu_data(m->extcpu).topo.initial_apicid;
129 m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP);
130 m->ppin = cpu_data(m->extcpu).ppin;
131 m->microcode = boot_cpu_data.microcode;
134 DEFINE_PER_CPU(struct mce, injectm);
135 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
137 void mce_log(struct mce *m)
139 if (!mce_gen_pool_add(m))
140 irq_work_queue(&mce_irq_work);
142 EXPORT_SYMBOL_GPL(mce_log);
144 void mce_register_decode_chain(struct notifier_block *nb)
146 if (WARN_ON(nb->priority < MCE_PRIO_LOWEST ||
147 nb->priority > MCE_PRIO_HIGHEST))
150 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
152 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
154 void mce_unregister_decode_chain(struct notifier_block *nb)
156 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
158 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
160 static void __print_mce(struct mce *m)
162 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
164 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
165 m->mcgstatus, m->bank, m->status);
168 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
169 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
172 if (m->cs == __KERNEL_CS)
173 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
177 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
179 pr_cont("ADDR %llx ", m->addr);
181 pr_cont("MISC %llx ", m->misc);
183 pr_cont("PPIN %llx ", m->ppin);
185 if (mce_flags.smca) {
187 pr_cont("SYND %llx ", m->synd);
189 pr_cont("IPID %llx ", m->ipid);
195 * Note this output is parsed by external tools and old fields
196 * should not be changed.
198 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
199 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
203 static void print_mce(struct mce *m)
207 if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
208 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
211 #define PANIC_TIMEOUT 5 /* 5 seconds */
213 static atomic_t mce_panicked;
215 static int fake_panic;
216 static atomic_t mce_fake_panicked;
218 /* Panic in progress. Enable interrupts and wait for final IPI */
219 static void wait_for_panic(void)
221 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
225 while (timeout-- > 0)
227 if (panic_timeout == 0)
228 panic_timeout = mca_cfg.panic_timeout;
229 panic("Panicing machine check CPU died");
232 static const char *mce_dump_aux_info(struct mce *m)
234 if (boot_cpu_has_bug(X86_BUG_TDX_PW_MCE))
235 return tdx_dump_mce_info(m);
240 static noinstr void mce_panic(const char *msg, struct mce *final, char *exp)
242 struct llist_node *pending;
243 struct mce_evt_llist *l;
248 * Allow instrumentation around external facilities usage. Not that it
249 * matters a whole lot since the machine is going to panic anyway.
251 instrumentation_begin();
255 * Make sure only one CPU runs in machine check panic
257 if (atomic_inc_return(&mce_panicked) > 1)
264 /* Don't log too much for fake panic */
265 if (atomic_inc_return(&mce_fake_panicked) > 1)
268 pending = mce_gen_pool_prepare_records();
269 /* First print corrected ones that are still unlogged */
270 llist_for_each_entry(l, pending, llnode) {
271 struct mce *m = &l->mce;
272 if (!(m->status & MCI_STATUS_UC)) {
275 apei_err = apei_write_mce(m);
278 /* Now print uncorrected but with the final one last */
279 llist_for_each_entry(l, pending, llnode) {
280 struct mce *m = &l->mce;
281 if (!(m->status & MCI_STATUS_UC))
283 if (!final || mce_cmp(m, final)) {
286 apei_err = apei_write_mce(m);
292 apei_err = apei_write_mce(final);
295 pr_emerg(HW_ERR "Machine check: %s\n", exp);
297 memmsg = mce_dump_aux_info(final);
299 pr_emerg(HW_ERR "Machine check: %s\n", memmsg);
302 if (panic_timeout == 0)
303 panic_timeout = mca_cfg.panic_timeout;
306 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
309 instrumentation_end();
312 /* Support code for software error injection */
314 static int msr_to_offset(u32 msr)
316 unsigned bank = __this_cpu_read(injectm.bank);
318 if (msr == mca_cfg.rip_msr)
319 return offsetof(struct mce, ip);
320 if (msr == mca_msr_reg(bank, MCA_STATUS))
321 return offsetof(struct mce, status);
322 if (msr == mca_msr_reg(bank, MCA_ADDR))
323 return offsetof(struct mce, addr);
324 if (msr == mca_msr_reg(bank, MCA_MISC))
325 return offsetof(struct mce, misc);
326 if (msr == MSR_IA32_MCG_STATUS)
327 return offsetof(struct mce, mcgstatus);
331 void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr)
334 pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n",
335 (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax,
336 regs->ip, (void *)regs->ip);
338 pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n",
339 (unsigned int)regs->cx, regs->ip, (void *)regs->ip);
342 show_stack_regs(regs);
344 panic("MCA architectural violation!\n");
350 /* MSR access wrappers used for error injection */
351 noinstr u64 mce_rdmsrl(u32 msr)
353 DECLARE_ARGS(val, low, high);
355 if (__this_cpu_read(injectm.finished)) {
359 instrumentation_begin();
361 offset = msr_to_offset(msr);
365 ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
367 instrumentation_end();
373 * RDMSR on MCA MSRs should not fault. If they do, this is very much an
374 * architectural violation and needs to be reported to hw vendor. Panic
375 * the box to not allow any further progress.
377 asm volatile("1: rdmsr\n"
379 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR_IN_MCE)
380 : EAX_EDX_RET(val, low, high) : "c" (msr));
383 return EAX_EDX_VAL(val, low, high);
386 static noinstr void mce_wrmsrl(u32 msr, u64 v)
390 if (__this_cpu_read(injectm.finished)) {
393 instrumentation_begin();
395 offset = msr_to_offset(msr);
397 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
399 instrumentation_end();
405 high = (u32)(v >> 32);
407 /* See comment in mce_rdmsrl() */
408 asm volatile("1: wrmsr\n"
410 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR_IN_MCE)
411 : : "c" (msr), "a"(low), "d" (high) : "memory");
415 * Collect all global (w.r.t. this processor) status about this machine
416 * check into our "mce" struct so that we can use it later to assess
417 * the severity of the problem as we read per-bank specific details.
419 static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs)
422 * Enable instrumentation around mce_setup() which calls external
425 instrumentation_begin();
427 instrumentation_end();
429 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
432 * Get the address of the instruction at the time of
433 * the machine check error.
435 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
440 * When in VM86 mode make the cs look like ring 3
441 * always. This is a lie, but it's better than passing
442 * the additional vm86 bit around everywhere.
444 if (v8086_mode(regs))
447 /* Use accurate RIP reporting if available. */
449 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
453 int mce_available(struct cpuinfo_x86 *c)
455 if (mca_cfg.disabled)
457 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
460 static void mce_schedule_work(void)
462 if (!mce_gen_pool_empty())
463 schedule_work(&mce_work);
466 static void mce_irq_work_cb(struct irq_work *entry)
471 bool mce_usable_address(struct mce *m)
473 if (!(m->status & MCI_STATUS_ADDRV))
476 switch (m->cpuvendor) {
478 return amd_mce_usable_address(m);
480 case X86_VENDOR_INTEL:
481 case X86_VENDOR_ZHAOXIN:
482 return intel_mce_usable_address(m);
488 EXPORT_SYMBOL_GPL(mce_usable_address);
490 bool mce_is_memory_error(struct mce *m)
492 switch (m->cpuvendor) {
494 case X86_VENDOR_HYGON:
495 return amd_mce_is_memory_error(m);
497 case X86_VENDOR_INTEL:
498 case X86_VENDOR_ZHAOXIN:
500 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
502 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
503 * indicating a memory error. Bit 8 is used for indicating a
504 * cache hierarchy error. The combination of bit 2 and bit 3
505 * is used for indicating a `generic' cache hierarchy error
506 * But we can't just blindly check the above bits, because if
507 * bit 11 is set, then it is a bus/interconnect error - and
508 * either way the above bits just gives more detail on what
509 * bus/interconnect error happened. Note that bit 12 can be
510 * ignored, as it's the "filter" bit.
512 return (m->status & 0xef80) == BIT(7) ||
513 (m->status & 0xef00) == BIT(8) ||
514 (m->status & 0xeffc) == 0xc;
520 EXPORT_SYMBOL_GPL(mce_is_memory_error);
522 static bool whole_page(struct mce *m)
524 if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV))
527 return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT;
530 bool mce_is_correctable(struct mce *m)
532 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
535 if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
538 if (m->status & MCI_STATUS_UC)
543 EXPORT_SYMBOL_GPL(mce_is_correctable);
545 static int mce_early_notifier(struct notifier_block *nb, unsigned long val,
548 struct mce *m = (struct mce *)data;
553 /* Emit the trace record: */
556 set_bit(0, &mce_need_notify);
563 static struct notifier_block early_nb = {
564 .notifier_call = mce_early_notifier,
565 .priority = MCE_PRIO_EARLY,
568 static int uc_decode_notifier(struct notifier_block *nb, unsigned long val,
571 struct mce *mce = (struct mce *)data;
574 if (!mce || !mce_usable_address(mce))
577 if (mce->severity != MCE_AO_SEVERITY &&
578 mce->severity != MCE_DEFERRED_SEVERITY)
581 pfn = (mce->addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT;
582 if (!memory_failure(pfn, 0)) {
584 mce->kflags |= MCE_HANDLED_UC;
590 static struct notifier_block mce_uc_nb = {
591 .notifier_call = uc_decode_notifier,
592 .priority = MCE_PRIO_UC,
595 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
598 struct mce *m = (struct mce *)data;
603 if (mca_cfg.print_all || !m->kflags)
609 static struct notifier_block mce_default_nb = {
610 .notifier_call = mce_default_notifier,
611 /* lowest prio, we want it to run last. */
612 .priority = MCE_PRIO_LOWEST,
616 * Read ADDR and MISC registers.
618 static noinstr void mce_read_aux(struct mce *m, int i)
620 if (m->status & MCI_STATUS_MISCV)
621 m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC));
623 if (m->status & MCI_STATUS_ADDRV) {
624 m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR));
627 * Mask the reported address by the reported granularity.
629 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
630 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
635 smca_extract_err_addr(m);
638 if (mce_flags.smca) {
639 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
641 if (m->status & MCI_STATUS_SYNDV)
642 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
646 DEFINE_PER_CPU(unsigned, mce_poll_count);
649 * Poll for corrected events or events that happened before reset.
650 * Those are just logged through /dev/mcelog.
652 * This is executed in standard interrupt context.
654 * Note: spec recommends to panic for fatal unsignalled
655 * errors here. However this would be quite problematic --
656 * we would need to reimplement the Monarch handling and
657 * it would mess up the exclusion between exception handler
658 * and poll handler -- * so we skip this for now.
659 * These cases should not happen anyways, or only when the CPU
660 * is already totally * confused. In this case it's likely it will
661 * not fully execute the machine check handler either.
663 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
665 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
666 bool error_seen = false;
670 this_cpu_inc(mce_poll_count);
672 mce_gather_info(&m, NULL);
674 if (flags & MCP_TIMESTAMP)
677 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
678 if (!mce_banks[i].ctl || !test_bit(i, *b))
686 m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
688 /* If this entry is not valid, ignore it */
689 if (!(m.status & MCI_STATUS_VAL))
693 * If we are logging everything (at CPU online) or this
694 * is a corrected error, then we must log it.
696 if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
700 * Newer Intel systems that support software error
701 * recovery need to make additional checks. Other
702 * CPUs should skip over uncorrected errors, but log
706 if (m.status & MCI_STATUS_UC)
711 /* Log "not enabled" (speculative) errors */
712 if (!(m.status & MCI_STATUS_EN))
716 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
717 * UC == 1 && PCC == 0 && S == 0
719 if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
723 * Skip anything else. Presumption is that our read of this
724 * bank is racing with a machine check. Leave the log alone
725 * for do_machine_check() to deal with it.
732 if (flags & MCP_DONTLOG)
736 m.severity = mce_severity(&m, NULL, NULL, false);
738 * Don't get the IP here because it's unlikely to
739 * have anything to do with the actual error location.
742 if (mca_cfg.dont_log_ce && !mce_usable_address(&m))
745 if (flags & MCP_QUEUE_LOG)
746 mce_gen_pool_add(&m);
752 * Clear state for this bank.
754 mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
758 * Don't clear MCG_STATUS here because it's only defined for
766 EXPORT_SYMBOL_GPL(machine_check_poll);
769 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
770 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
771 * Vol 3B Table 15-20). But this confuses both the code that determines
772 * whether the machine check occurred in kernel or user mode, and also
773 * the severity assessment code. Pretend that EIPV was set, and take the
774 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
776 static __always_inline void
777 quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
781 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
783 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
784 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
785 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
787 (MCI_STATUS_UC|MCI_STATUS_EN|
788 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
789 MCI_STATUS_AR|MCACOD_INSTR))
792 m->mcgstatus |= MCG_STATUS_EIPV;
798 * Disable fast string copy and return from the MCE handler upon the first SRAR
799 * MCE on bank 1 due to a CPU erratum on Intel Skylake/Cascade Lake/Cooper Lake
801 * The fast string copy instructions ("REP; MOVS*") could consume an
802 * uncorrectable memory error in the cache line _right after_ the desired region
803 * to copy and raise an MCE with RIP pointing to the instruction _after_ the
805 * This mitigation addresses the issue completely with the caveat of performance
806 * degradation on the CPU affected. This is still better than the OS crashing on
807 * MCEs raised on an irrelevant process due to "REP; MOVS*" accesses from a
808 * kernel context (e.g., copy_page).
810 * Returns true when fast string copy on CPU has been disabled.
812 static noinstr bool quirk_skylake_repmov(void)
814 u64 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
815 u64 misc_enable = mce_rdmsrl(MSR_IA32_MISC_ENABLE);
819 * Apply the quirk only to local machine checks, i.e., no broadcast
822 if (!(mcgstatus & MCG_STATUS_LMCES) ||
823 !(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING))
826 mc1_status = mce_rdmsrl(MSR_IA32_MCx_STATUS(1));
828 /* Check for a software-recoverable data fetch error. */
830 (MCI_STATUS_VAL | MCI_STATUS_OVER | MCI_STATUS_UC | MCI_STATUS_EN |
831 MCI_STATUS_ADDRV | MCI_STATUS_MISCV | MCI_STATUS_PCC |
832 MCI_STATUS_AR | MCI_STATUS_S)) ==
833 (MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
834 MCI_STATUS_ADDRV | MCI_STATUS_MISCV |
835 MCI_STATUS_AR | MCI_STATUS_S)) {
836 misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
837 mce_wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
838 mce_wrmsrl(MSR_IA32_MCx_STATUS(1), 0);
840 instrumentation_begin();
841 pr_err_once("Erratum detected, disable fast string copy instructions.\n");
842 instrumentation_end();
851 * Some Zen-based Instruction Fetch Units set EIPV=RIPV=0 on poison consumption
852 * errors. This means mce_gather_info() will not save the "ip" and "cs" registers.
854 * However, the context is still valid, so save the "cs" register for later use.
856 * The "ip" register is truly unknown, so don't save it or fixup EIPV/RIPV.
858 * The Instruction Fetch Unit is at MCA bank 1 for all affected systems.
860 static __always_inline void quirk_zen_ifu(int bank, struct mce *m, struct pt_regs *regs)
864 if (!(m->status & MCI_STATUS_POISON))
871 * Do a quick check if any of the events requires a panic.
872 * This decides if we keep the events around or clear them.
874 static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
875 struct pt_regs *regs)
880 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
881 m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
882 if (!(m->status & MCI_STATUS_VAL))
885 arch___set_bit(i, validp);
886 if (mce_flags.snb_ifu_quirk)
887 quirk_sandybridge_ifu(i, m, regs);
889 if (mce_flags.zen_ifu_quirk)
890 quirk_zen_ifu(i, m, regs);
893 if (mce_severity(m, regs, &tmp, true) >= MCE_PANIC_SEVERITY) {
903 * Variable to establish order between CPUs while scanning.
904 * Each CPU spins initially until executing is equal its number.
906 static atomic_t mce_executing;
909 * Defines order of CPUs on entry. First CPU becomes Monarch.
911 static atomic_t mce_callin;
914 * Track which CPUs entered the MCA broadcast synchronization and which not in
915 * order to print holdouts.
917 static cpumask_t mce_missing_cpus = CPU_MASK_ALL;
920 * Check if a timeout waiting for other CPUs happened.
922 static noinstr int mce_timed_out(u64 *t, const char *msg)
926 /* Enable instrumentation around calls to external facilities */
927 instrumentation_begin();
930 * The others already did panic for some reason.
931 * Bail out like in a timeout.
932 * rmb() to tell the compiler that system_state
933 * might have been modified by someone else.
936 if (atomic_read(&mce_panicked))
938 if (!mca_cfg.monarch_timeout)
940 if ((s64)*t < SPINUNIT) {
941 if (cpumask_and(&mce_missing_cpus, cpu_online_mask, &mce_missing_cpus))
942 pr_emerg("CPUs not responding to MCE broadcast (may include false positives): %*pbl\n",
943 cpumask_pr_args(&mce_missing_cpus));
944 mce_panic(msg, NULL, NULL);
952 touch_nmi_watchdog();
954 instrumentation_end();
960 * The Monarch's reign. The Monarch is the CPU who entered
961 * the machine check handler first. It waits for the others to
962 * raise the exception too and then grades them. When any
963 * error is fatal panic. Only then let the others continue.
965 * The other CPUs entering the MCE handler will be controlled by the
966 * Monarch. They are called Subjects.
968 * This way we prevent any potential data corruption in a unrecoverable case
969 * and also makes sure always all CPU's errors are examined.
971 * Also this detects the case of a machine check event coming from outer
972 * space (not detected by any CPUs) In this case some external agent wants
973 * us to shut down, so panic too.
975 * The other CPUs might still decide to panic if the handler happens
976 * in a unrecoverable place, but in this case the system is in a semi-stable
977 * state and won't corrupt anything by itself. It's ok to let the others
978 * continue for a bit first.
980 * All the spin loops have timeouts; when a timeout happens a CPU
981 * typically elects itself to be Monarch.
983 static void mce_reign(void)
986 struct mce *m = NULL;
987 int global_worst = 0;
991 * This CPU is the Monarch and the other CPUs have run
992 * through their handlers.
993 * Grade the severity of the errors of all the CPUs.
995 for_each_possible_cpu(cpu) {
996 struct mce *mtmp = &per_cpu(mces_seen, cpu);
998 if (mtmp->severity > global_worst) {
999 global_worst = mtmp->severity;
1000 m = &per_cpu(mces_seen, cpu);
1005 * Cannot recover? Panic here then.
1006 * This dumps all the mces in the log buffer and stops the
1009 if (m && global_worst >= MCE_PANIC_SEVERITY) {
1010 /* call mce_severity() to get "msg" for panic */
1011 mce_severity(m, NULL, &msg, true);
1012 mce_panic("Fatal machine check", m, msg);
1016 * For UC somewhere we let the CPU who detects it handle it.
1017 * Also must let continue the others, otherwise the handling
1018 * CPU could deadlock on a lock.
1022 * No machine check event found. Must be some external
1023 * source or one CPU is hung. Panic.
1025 if (global_worst <= MCE_KEEP_SEVERITY)
1026 mce_panic("Fatal machine check from unknown source", NULL, NULL);
1029 * Now clear all the mces_seen so that they don't reappear on
1032 for_each_possible_cpu(cpu)
1033 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
1036 static atomic_t global_nwo;
1039 * Start of Monarch synchronization. This waits until all CPUs have
1040 * entered the exception handler and then determines if any of them
1041 * saw a fatal event that requires panic. Then it executes them
1042 * in the entry order.
1043 * TBD double check parallel CPU hotunplug
1045 static noinstr int mce_start(int *no_way_out)
1047 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1048 int order, ret = -1;
1053 raw_atomic_add(*no_way_out, &global_nwo);
1055 * Rely on the implied barrier below, such that global_nwo
1056 * is updated before mce_callin.
1058 order = raw_atomic_inc_return(&mce_callin);
1059 arch_cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus);
1061 /* Enable instrumentation around calls to external facilities */
1062 instrumentation_begin();
1065 * Wait for everyone.
1067 while (raw_atomic_read(&mce_callin) != num_online_cpus()) {
1068 if (mce_timed_out(&timeout,
1069 "Timeout: Not all CPUs entered broadcast exception handler")) {
1070 raw_atomic_set(&global_nwo, 0);
1077 * mce_callin should be read before global_nwo
1083 * Monarch: Starts executing now, the others wait.
1085 raw_atomic_set(&mce_executing, 1);
1088 * Subject: Now start the scanning loop one by one in
1089 * the original callin order.
1090 * This way when there are any shared banks it will be
1091 * only seen by one CPU before cleared, avoiding duplicates.
1093 while (raw_atomic_read(&mce_executing) < order) {
1094 if (mce_timed_out(&timeout,
1095 "Timeout: Subject CPUs unable to finish machine check processing")) {
1096 raw_atomic_set(&global_nwo, 0);
1104 * Cache the global no_way_out state.
1106 *no_way_out = raw_atomic_read(&global_nwo);
1111 instrumentation_end();
1117 * Synchronize between CPUs after main scanning loop.
1118 * This invokes the bulk of the Monarch processing.
1120 static noinstr int mce_end(int order)
1122 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1125 /* Allow instrumentation around external facilities. */
1126 instrumentation_begin();
1134 * Allow others to run.
1136 atomic_inc(&mce_executing);
1140 * Monarch: Wait for everyone to go through their scanning
1143 while (atomic_read(&mce_executing) <= num_online_cpus()) {
1144 if (mce_timed_out(&timeout,
1145 "Timeout: Monarch CPU unable to finish machine check processing"))
1155 * Subject: Wait for Monarch to finish.
1157 while (atomic_read(&mce_executing) != 0) {
1158 if (mce_timed_out(&timeout,
1159 "Timeout: Monarch CPU did not finish machine check processing"))
1165 * Don't reset anything. That's done by the Monarch.
1172 * Reset all global state.
1175 atomic_set(&global_nwo, 0);
1176 atomic_set(&mce_callin, 0);
1177 cpumask_setall(&mce_missing_cpus);
1181 * Let others run again.
1183 atomic_set(&mce_executing, 0);
1186 instrumentation_end();
1191 static __always_inline void mce_clear_state(unsigned long *toclear)
1195 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1196 if (arch_test_bit(i, toclear))
1197 mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
1202 * Cases where we avoid rendezvous handler timeout:
1203 * 1) If this CPU is offline.
1205 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1206 * skip those CPUs which remain looping in the 1st kernel - see
1207 * crash_nmi_callback().
1209 * Note: there still is a small window between kexec-ing and the new,
1210 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1211 * might not get handled properly.
1213 static noinstr bool mce_check_crashing_cpu(void)
1215 unsigned int cpu = smp_processor_id();
1217 if (arch_cpu_is_offline(cpu) ||
1218 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1221 mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS);
1223 if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
1224 if (mcgstatus & MCG_STATUS_LMCES)
1228 if (mcgstatus & MCG_STATUS_RIPV) {
1229 __wrmsr(MSR_IA32_MCG_STATUS, 0, 0);
1236 static __always_inline int
1237 __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final,
1238 unsigned long *toclear, unsigned long *valid_banks, int no_way_out,
1241 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1242 struct mca_config *cfg = &mca_cfg;
1243 int severity, i, taint = 0;
1245 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1246 arch___clear_bit(i, toclear);
1247 if (!arch_test_bit(i, valid_banks))
1250 if (!mce_banks[i].ctl)
1257 m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
1258 if (!(m->status & MCI_STATUS_VAL))
1262 * Corrected or non-signaled errors are handled by
1263 * machine_check_poll(). Leave them alone, unless this panics.
1265 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1269 /* Set taint even when machine check was not enabled. */
1272 severity = mce_severity(m, regs, NULL, true);
1275 * When machine check was for corrected/deferred handler don't
1276 * touch, unless we're panicking.
1278 if ((severity == MCE_KEEP_SEVERITY ||
1279 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1282 arch___set_bit(i, toclear);
1284 /* Machine check event was not enabled. Clear, but ignore. */
1285 if (severity == MCE_NO_SEVERITY)
1290 /* assuming valid severity level != 0 */
1291 m->severity = severity;
1294 * Enable instrumentation around the mce_log() call which is
1295 * done in #MC context, where instrumentation is disabled.
1297 instrumentation_begin();
1299 instrumentation_end();
1301 if (severity > *worst) {
1307 /* mce_clear_state will clear *final, save locally for use later */
1313 static void kill_me_now(struct callback_head *ch)
1315 struct task_struct *p = container_of(ch, struct task_struct, mce_kill_me);
1321 static void kill_me_maybe(struct callback_head *cb)
1323 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1324 int flags = MF_ACTION_REQUIRED;
1329 pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr);
1332 flags |= MF_MUST_KILL;
1334 pfn = (p->mce_addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT;
1335 ret = memory_failure(pfn, flags);
1337 set_mce_nospec(pfn);
1343 * -EHWPOISON from memory_failure() means that it already sent SIGBUS
1344 * to the current process with the proper error info,
1345 * -EOPNOTSUPP means hwpoison_filter() filtered the error event,
1347 * In both cases, no further processing is required.
1349 if (ret == -EHWPOISON || ret == -EOPNOTSUPP)
1352 pr_err("Memory error not recovered");
1356 static void kill_me_never(struct callback_head *cb)
1358 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1362 pr_err("Kernel accessed poison in user space at %llx\n", p->mce_addr);
1363 pfn = (p->mce_addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT;
1364 if (!memory_failure(pfn, 0))
1365 set_mce_nospec(pfn);
1368 static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callback_head *))
1370 int count = ++current->mce_count;
1372 /* First call, save all the details */
1374 current->mce_addr = m->addr;
1375 current->mce_kflags = m->kflags;
1376 current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV);
1377 current->mce_whole_page = whole_page(m);
1378 current->mce_kill_me.func = func;
1381 /* Ten is likely overkill. Don't expect more than two faults before task_work() */
1383 mce_panic("Too many consecutive machine checks while accessing user data", m, msg);
1385 /* Second or later call, make sure page address matches the one from first call */
1386 if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT))
1387 mce_panic("Consecutive machine checks to different user pages", m, msg);
1389 /* Do not call task_work_add() more than once */
1393 task_work_add(current, ¤t->mce_kill_me, TWA_RESUME);
1396 /* Handle unconfigured int18 (should never happen) */
1397 static noinstr void unexpected_machine_check(struct pt_regs *regs)
1399 instrumentation_begin();
1400 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1401 smp_processor_id());
1402 instrumentation_end();
1406 * The actual machine check handler. This only handles real exceptions when
1407 * something got corrupted coming in through int 18.
1409 * This is executed in #MC context not subject to normal locking rules.
1410 * This implies that most kernel services cannot be safely used. Don't even
1411 * think about putting a printk in there!
1413 * On Intel systems this is entered on all CPUs in parallel through
1414 * MCE broadcast. However some CPUs might be broken beyond repair,
1415 * so be always careful when synchronizing with others.
1417 * Tracing and kprobes are disabled: if we interrupted a kernel context
1418 * with IF=1, we need to minimize stack usage. There are also recursion
1419 * issues: if the machine check was due to a failure of the memory
1420 * backing the user stack, tracing that reads the user stack will cause
1421 * potentially infinite recursion.
1423 * Currently, the #MC handler calls out to a number of external facilities
1424 * and, therefore, allows instrumentation around them. The optimal thing to
1425 * have would be to do the absolutely minimal work required in #MC context
1426 * and have instrumentation disabled only around that. Further processing can
1427 * then happen in process context where instrumentation is allowed. Achieving
1428 * that requires careful auditing and modifications. Until then, the code
1429 * allows instrumentation temporarily, where required. *
1431 noinstr void do_machine_check(struct pt_regs *regs)
1433 int worst = 0, order, no_way_out, kill_current_task, lmce, taint = 0;
1434 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS) = { 0 };
1435 DECLARE_BITMAP(toclear, MAX_NR_BANKS) = { 0 };
1436 struct mce m, *final;
1439 if (unlikely(mce_flags.p5))
1440 return pentium_machine_check(regs);
1441 else if (unlikely(mce_flags.winchip))
1442 return winchip_machine_check(regs);
1443 else if (unlikely(!mca_cfg.initialized))
1444 return unexpected_machine_check(regs);
1446 if (mce_flags.skx_repmov_quirk && quirk_skylake_repmov())
1450 * Establish sequential order between the CPUs entering the machine
1456 * If no_way_out gets set, there is no safe way to recover from this
1462 * If kill_current_task is not set, there might be a way to recover from this
1465 kill_current_task = 0;
1468 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1473 this_cpu_inc(mce_exception_count);
1475 mce_gather_info(&m, regs);
1478 final = this_cpu_ptr(&mces_seen);
1481 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1486 * When no restart IP might need to kill or panic.
1487 * Assume the worst for now, but if we find the
1488 * severity is MCE_AR_SEVERITY we have other options.
1490 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1491 kill_current_task = 1;
1493 * Check if this MCE is signaled to only this logical processor,
1494 * on Intel, Zhaoxin only.
1496 if (m.cpuvendor == X86_VENDOR_INTEL ||
1497 m.cpuvendor == X86_VENDOR_ZHAOXIN)
1498 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1501 * Local machine check may already know that we have to panic.
1502 * Broadcast machine check begins rendezvous in mce_start()
1503 * Go through all banks in exclusion of the other CPUs. This way we
1504 * don't report duplicated events on shared banks because the first one
1505 * to see it will clear it.
1509 mce_panic("Fatal local machine check", &m, msg);
1511 order = mce_start(&no_way_out);
1514 taint = __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst);
1517 mce_clear_state(toclear);
1520 * Do most of the synchronization with other CPUs.
1521 * When there's any problem use only local no_way_out state.
1524 if (mce_end(order) < 0) {
1526 no_way_out = worst >= MCE_PANIC_SEVERITY;
1529 mce_panic("Fatal machine check on current CPU", &m, msg);
1533 * If there was a fatal machine check we should have
1534 * already called mce_panic earlier in this function.
1535 * Since we re-read the banks, we might have found
1536 * something new. Check again to see if we found a
1537 * fatal error. We call "mce_severity()" again to
1538 * make sure we have the right "msg".
1540 if (worst >= MCE_PANIC_SEVERITY) {
1541 mce_severity(&m, regs, &msg, true);
1542 mce_panic("Local fatal machine check!", &m, msg);
1547 * Enable instrumentation around the external facilities like task_work_add()
1548 * (via queue_task_work()), fixup_exception() etc. For now, that is. Fixing this
1549 * properly would need a lot more involved reorganization.
1551 instrumentation_begin();
1554 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1556 if (worst != MCE_AR_SEVERITY && !kill_current_task)
1559 /* Fault was in user mode and we need to take some action */
1560 if ((m.cs & 3) == 3) {
1561 /* If this triggers there is no way to recover. Die hard. */
1562 BUG_ON(!on_thread_stack() || !user_mode(regs));
1564 if (!mce_usable_address(&m))
1565 queue_task_work(&m, msg, kill_me_now);
1567 queue_task_work(&m, msg, kill_me_maybe);
1571 * Handle an MCE which has happened in kernel space but from
1572 * which the kernel can recover: ex_has_fault_handler() has
1573 * already verified that the rIP at which the error happened is
1574 * a rIP from which the kernel can recover (by jumping to
1575 * recovery code specified in _ASM_EXTABLE_FAULT()) and the
1576 * corresponding exception handler which would do that is the
1579 if (m.kflags & MCE_IN_KERNEL_RECOV) {
1580 if (!fixup_exception(regs, X86_TRAP_MC, 0, 0))
1581 mce_panic("Failed kernel mode recovery", &m, msg);
1584 if (m.kflags & MCE_IN_KERNEL_COPYIN)
1585 queue_task_work(&m, msg, kill_me_never);
1589 instrumentation_end();
1592 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1594 EXPORT_SYMBOL_GPL(do_machine_check);
1596 #ifndef CONFIG_MEMORY_FAILURE
1597 int memory_failure(unsigned long pfn, int flags)
1599 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1600 BUG_ON(flags & MF_ACTION_REQUIRED);
1601 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1602 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1610 * Periodic polling timer for "silent" machine check errors. If the
1611 * poller finds an MCE, poll 2x faster. When the poller finds no more
1612 * errors, poll 2x slower (up to check_interval seconds).
1614 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1616 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1617 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1619 static unsigned long mce_adjust_timer_default(unsigned long interval)
1624 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1626 static void __start_timer(struct timer_list *t, unsigned long interval)
1628 unsigned long when = jiffies + interval;
1629 unsigned long flags;
1631 local_irq_save(flags);
1633 if (!timer_pending(t) || time_before(when, t->expires))
1634 mod_timer(t, round_jiffies(when));
1636 local_irq_restore(flags);
1639 static void mc_poll_banks_default(void)
1641 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1644 void (*mc_poll_banks)(void) = mc_poll_banks_default;
1646 static void mce_timer_fn(struct timer_list *t)
1648 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1651 WARN_ON(cpu_t != t);
1653 iv = __this_cpu_read(mce_next_interval);
1655 if (mce_available(this_cpu_ptr(&cpu_info))) {
1658 if (mce_intel_cmci_poll()) {
1659 iv = mce_adjust_timer(iv);
1665 * Alert userspace if needed. If we logged an MCE, reduce the polling
1666 * interval, otherwise increase the polling interval.
1668 if (mce_notify_irq())
1669 iv = max(iv / 2, (unsigned long) HZ/100);
1671 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1674 __this_cpu_write(mce_next_interval, iv);
1675 __start_timer(t, iv);
1679 * Ensure that the timer is firing in @interval from now.
1681 void mce_timer_kick(unsigned long interval)
1683 struct timer_list *t = this_cpu_ptr(&mce_timer);
1684 unsigned long iv = __this_cpu_read(mce_next_interval);
1686 __start_timer(t, interval);
1689 __this_cpu_write(mce_next_interval, interval);
1692 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1693 static void mce_timer_delete_all(void)
1697 for_each_online_cpu(cpu)
1698 del_timer_sync(&per_cpu(mce_timer, cpu));
1702 * Notify the user(s) about new machine check events.
1703 * Can be called from interrupt context, but not from machine check/NMI
1706 int mce_notify_irq(void)
1708 /* Not more than two messages every minute */
1709 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1711 if (test_and_clear_bit(0, &mce_need_notify)) {
1714 if (__ratelimit(&ratelimit))
1715 pr_info(HW_ERR "Machine check events logged\n");
1721 EXPORT_SYMBOL_GPL(mce_notify_irq);
1723 static void __mcheck_cpu_mce_banks_init(void)
1725 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1726 u8 n_banks = this_cpu_read(mce_num_banks);
1729 for (i = 0; i < n_banks; i++) {
1730 struct mce_bank *b = &mce_banks[i];
1733 * Init them all, __mcheck_cpu_apply_quirks() is going to apply
1734 * the required vendor quirks before
1735 * __mcheck_cpu_init_clear_banks() does the final bank setup.
1743 * Initialize Machine Checks for a CPU.
1745 static void __mcheck_cpu_cap_init(void)
1750 rdmsrl(MSR_IA32_MCG_CAP, cap);
1752 b = cap & MCG_BANKCNT_MASK;
1754 if (b > MAX_NR_BANKS) {
1755 pr_warn("CPU%d: Using only %u machine check banks out of %u\n",
1756 smp_processor_id(), MAX_NR_BANKS, b);
1760 this_cpu_write(mce_num_banks, b);
1762 __mcheck_cpu_mce_banks_init();
1764 /* Use accurate RIP reporting if available. */
1765 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1766 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1768 if (cap & MCG_SER_P)
1772 static void __mcheck_cpu_init_generic(void)
1774 enum mcp_flags m_fl = 0;
1775 mce_banks_t all_banks;
1778 if (!mca_cfg.bootlog)
1782 * Log the machine checks left over from the previous reset. Log them
1783 * only, do not start processing them. That will happen in mcheck_late_init()
1784 * when all consumers have been registered on the notifier chain.
1786 bitmap_fill(all_banks, MAX_NR_BANKS);
1787 machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks);
1789 cr4_set_bits(X86_CR4_MCE);
1791 rdmsrl(MSR_IA32_MCG_CAP, cap);
1792 if (cap & MCG_CTL_P)
1793 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1796 static void __mcheck_cpu_init_clear_banks(void)
1798 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1801 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1802 struct mce_bank *b = &mce_banks[i];
1806 wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl);
1807 wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
1812 * Do a final check to see if there are any unused/RAZ banks.
1814 * This must be done after the banks have been initialized and any quirks have
1817 * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs.
1818 * Otherwise, a user who disables a bank will not be able to re-enable it
1819 * without a system reboot.
1821 static void __mcheck_cpu_check_banks(void)
1823 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1827 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1828 struct mce_bank *b = &mce_banks[i];
1833 rdmsrl(mca_msr_reg(i, MCA_CTL), msrval);
1838 /* Add per CPU specific workarounds here */
1839 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1841 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1842 struct mca_config *cfg = &mca_cfg;
1844 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1845 pr_info("unknown CPU type - not enabling MCE support\n");
1849 /* This should be disabled by the BIOS, but isn't always */
1850 if (c->x86_vendor == X86_VENDOR_AMD) {
1851 if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
1853 * disable GART TBL walk error reporting, which
1854 * trips off incorrectly with the IOMMU & 3ware
1857 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1859 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1861 * Lots of broken BIOS around that don't clear them
1862 * by default and leave crap in there. Don't log:
1867 * Various K7s with broken bank 0 around. Always disable
1870 if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1871 mce_banks[0].ctl = 0;
1874 * overflow_recov is supported for F15h Models 00h-0fh
1875 * even though we don't have a CPUID bit for it.
1877 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1878 mce_flags.overflow_recov = 1;
1880 if (c->x86 >= 0x17 && c->x86 <= 0x1A)
1881 mce_flags.zen_ifu_quirk = 1;
1885 if (c->x86_vendor == X86_VENDOR_INTEL) {
1887 * SDM documents that on family 6 bank 0 should not be written
1888 * because it aliases to another special BIOS controlled
1890 * But it's not aliased anymore on model 0x1a+
1891 * Don't ignore bank 0 completely because there could be a
1892 * valid event later, merely don't write CTL0.
1895 if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1896 mce_banks[0].init = false;
1899 * All newer Intel systems support MCE broadcasting. Enable
1900 * synchronization with a one second timeout.
1902 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1903 cfg->monarch_timeout < 0)
1904 cfg->monarch_timeout = USEC_PER_SEC;
1907 * There are also broken BIOSes on some Pentium M and
1910 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1913 if (c->x86 == 6 && c->x86_model == 45)
1914 mce_flags.snb_ifu_quirk = 1;
1917 * Skylake, Cascacde Lake and Cooper Lake require a quirk on
1920 if (c->x86 == 6 && c->x86_model == INTEL_FAM6_SKYLAKE_X)
1921 mce_flags.skx_repmov_quirk = 1;
1924 if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
1926 * All newer Zhaoxin CPUs support MCE broadcasting. Enable
1927 * synchronization with a one second timeout.
1929 if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1930 if (cfg->monarch_timeout < 0)
1931 cfg->monarch_timeout = USEC_PER_SEC;
1935 if (cfg->monarch_timeout < 0)
1936 cfg->monarch_timeout = 0;
1937 if (cfg->bootlog != 0)
1938 cfg->panic_timeout = 30;
1943 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1948 switch (c->x86_vendor) {
1949 case X86_VENDOR_INTEL:
1950 intel_p5_mcheck_init(c);
1953 case X86_VENDOR_CENTAUR:
1954 winchip_mcheck_init(c);
1955 mce_flags.winchip = 1;
1965 * Init basic CPU features needed for early decoding of MCEs.
1967 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1969 if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
1970 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1971 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1972 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1973 mce_flags.amd_threshold = 1;
1977 static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1979 struct mca_config *cfg = &mca_cfg;
1982 * All newer Centaur CPUs support MCE broadcasting. Enable
1983 * synchronization with a one second timeout.
1985 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1987 if (cfg->monarch_timeout < 0)
1988 cfg->monarch_timeout = USEC_PER_SEC;
1992 static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
1994 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1997 * These CPUs have MCA bank 8 which reports only one error type called
1998 * SVAD (System View Address Decoder). The reporting of that error is
1999 * controlled by IA32_MC8.CTL.0.
2001 * If enabled, prefetching on these CPUs will cause SVAD MCE when
2002 * virtual machines start and result in a system panic. Always disable
2003 * bank 8 SVAD error by default.
2005 if ((c->x86 == 7 && c->x86_model == 0x1b) ||
2006 (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
2007 if (this_cpu_read(mce_num_banks) > 8)
2008 mce_banks[8].ctl = 0;
2013 mce_adjust_timer = cmci_intel_adjust_timer;
2016 static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
2021 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
2023 switch (c->x86_vendor) {
2024 case X86_VENDOR_INTEL:
2025 mce_intel_feature_init(c);
2026 mce_adjust_timer = cmci_intel_adjust_timer;
2029 case X86_VENDOR_AMD: {
2030 mce_amd_feature_init(c);
2034 case X86_VENDOR_HYGON:
2035 mce_hygon_feature_init(c);
2038 case X86_VENDOR_CENTAUR:
2039 mce_centaur_feature_init(c);
2042 case X86_VENDOR_ZHAOXIN:
2043 mce_zhaoxin_feature_init(c);
2051 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
2053 switch (c->x86_vendor) {
2054 case X86_VENDOR_INTEL:
2055 mce_intel_feature_clear(c);
2058 case X86_VENDOR_ZHAOXIN:
2059 mce_zhaoxin_feature_clear(c);
2067 static void mce_start_timer(struct timer_list *t)
2069 unsigned long iv = check_interval * HZ;
2071 if (mca_cfg.ignore_ce || !iv)
2074 this_cpu_write(mce_next_interval, iv);
2075 __start_timer(t, iv);
2078 static void __mcheck_cpu_setup_timer(void)
2080 struct timer_list *t = this_cpu_ptr(&mce_timer);
2082 timer_setup(t, mce_timer_fn, TIMER_PINNED);
2085 static void __mcheck_cpu_init_timer(void)
2087 struct timer_list *t = this_cpu_ptr(&mce_timer);
2089 timer_setup(t, mce_timer_fn, TIMER_PINNED);
2093 bool filter_mce(struct mce *m)
2095 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
2096 return amd_filter_mce(m);
2097 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2098 return intel_filter_mce(m);
2103 static __always_inline void exc_machine_check_kernel(struct pt_regs *regs)
2105 irqentry_state_t irq_state;
2107 WARN_ON_ONCE(user_mode(regs));
2110 * Only required when from kernel mode. See
2111 * mce_check_crashing_cpu() for details.
2113 if (mca_cfg.initialized && mce_check_crashing_cpu())
2116 irq_state = irqentry_nmi_enter(regs);
2118 do_machine_check(regs);
2120 irqentry_nmi_exit(regs, irq_state);
2123 static __always_inline void exc_machine_check_user(struct pt_regs *regs)
2125 irqentry_enter_from_user_mode(regs);
2127 do_machine_check(regs);
2129 irqentry_exit_to_user_mode(regs);
2132 #ifdef CONFIG_X86_64
2133 /* MCE hit kernel mode */
2134 DEFINE_IDTENTRY_MCE(exc_machine_check)
2138 dr7 = local_db_save();
2139 exc_machine_check_kernel(regs);
2140 local_db_restore(dr7);
2143 /* The user mode variant. */
2144 DEFINE_IDTENTRY_MCE_USER(exc_machine_check)
2148 dr7 = local_db_save();
2149 exc_machine_check_user(regs);
2150 local_db_restore(dr7);
2153 /* 32bit unified entry point */
2154 DEFINE_IDTENTRY_RAW(exc_machine_check)
2158 dr7 = local_db_save();
2159 if (user_mode(regs))
2160 exc_machine_check_user(regs);
2162 exc_machine_check_kernel(regs);
2163 local_db_restore(dr7);
2168 * Called for each booted CPU to set up machine checks.
2169 * Must be called with preempt off:
2171 void mcheck_cpu_init(struct cpuinfo_x86 *c)
2173 if (mca_cfg.disabled)
2176 if (__mcheck_cpu_ancient_init(c))
2179 if (!mce_available(c))
2182 __mcheck_cpu_cap_init();
2184 if (__mcheck_cpu_apply_quirks(c) < 0) {
2185 mca_cfg.disabled = 1;
2189 if (mce_gen_pool_init()) {
2190 mca_cfg.disabled = 1;
2191 pr_emerg("Couldn't allocate MCE records pool!\n");
2195 mca_cfg.initialized = 1;
2197 __mcheck_cpu_init_early(c);
2198 __mcheck_cpu_init_generic();
2199 __mcheck_cpu_init_vendor(c);
2200 __mcheck_cpu_init_clear_banks();
2201 __mcheck_cpu_check_banks();
2202 __mcheck_cpu_setup_timer();
2206 * Called for each booted CPU to clear some machine checks opt-ins
2208 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
2210 if (mca_cfg.disabled)
2213 if (!mce_available(c))
2217 * Possibly to clear general settings generic to x86
2218 * __mcheck_cpu_clear_generic(c);
2220 __mcheck_cpu_clear_vendor(c);
2224 static void __mce_disable_bank(void *arg)
2226 int bank = *((int *)arg);
2227 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
2228 cmci_disable_bank(bank);
2231 void mce_disable_bank(int bank)
2233 if (bank >= this_cpu_read(mce_num_banks)) {
2235 "Ignoring request to disable invalid MCA bank %d.\n",
2239 set_bit(bank, mce_banks_ce_disabled);
2240 on_each_cpu(__mce_disable_bank, &bank, 1);
2244 * mce=off Disables machine check
2245 * mce=no_cmci Disables CMCI
2246 * mce=no_lmce Disables LMCE
2247 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2248 * mce=print_all Print all machine check logs to console
2249 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2250 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2251 * monarchtimeout is how long to wait for other CPUs on machine
2252 * check, or 0 to not wait
2253 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
2255 * mce=nobootlog Don't log MCEs from before booting.
2256 * mce=bios_cmci_threshold Don't program the CMCI threshold
2257 * mce=recovery force enable copy_mc_fragile()
2259 static int __init mcheck_enable(char *str)
2261 struct mca_config *cfg = &mca_cfg;
2269 if (!strcmp(str, "off"))
2271 else if (!strcmp(str, "no_cmci"))
2272 cfg->cmci_disabled = true;
2273 else if (!strcmp(str, "no_lmce"))
2274 cfg->lmce_disabled = 1;
2275 else if (!strcmp(str, "dont_log_ce"))
2276 cfg->dont_log_ce = true;
2277 else if (!strcmp(str, "print_all"))
2278 cfg->print_all = true;
2279 else if (!strcmp(str, "ignore_ce"))
2280 cfg->ignore_ce = true;
2281 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2282 cfg->bootlog = (str[0] == 'b');
2283 else if (!strcmp(str, "bios_cmci_threshold"))
2284 cfg->bios_cmci_threshold = 1;
2285 else if (!strcmp(str, "recovery"))
2287 else if (isdigit(str[0]))
2288 get_option(&str, &(cfg->monarch_timeout));
2290 pr_info("mce argument %s ignored. Please use /sys\n", str);
2295 __setup("mce", mcheck_enable);
2297 int __init mcheck_init(void)
2299 mce_register_decode_chain(&early_nb);
2300 mce_register_decode_chain(&mce_uc_nb);
2301 mce_register_decode_chain(&mce_default_nb);
2303 INIT_WORK(&mce_work, mce_gen_pool_process);
2304 init_irq_work(&mce_irq_work, mce_irq_work_cb);
2310 * mce_syscore: PM support
2314 * Disable machine checks on suspend and shutdown. We can't really handle
2317 static void mce_disable_error_reporting(void)
2319 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2322 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2323 struct mce_bank *b = &mce_banks[i];
2326 wrmsrl(mca_msr_reg(i, MCA_CTL), 0);
2331 static void vendor_disable_error_reporting(void)
2334 * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
2335 * MSRs are socket-wide. Disabling them for just a single offlined CPU
2336 * is bad, since it will inhibit reporting for all shared resources on
2337 * the socket like the last level cache (LLC), the integrated memory
2338 * controller (iMC), etc.
2340 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
2341 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
2342 boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
2343 boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
2346 mce_disable_error_reporting();
2349 static int mce_syscore_suspend(void)
2351 vendor_disable_error_reporting();
2355 static void mce_syscore_shutdown(void)
2357 vendor_disable_error_reporting();
2361 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2362 * Only one CPU is active at this time, the others get re-added later using
2365 static void mce_syscore_resume(void)
2367 __mcheck_cpu_init_generic();
2368 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2369 __mcheck_cpu_init_clear_banks();
2372 static struct syscore_ops mce_syscore_ops = {
2373 .suspend = mce_syscore_suspend,
2374 .shutdown = mce_syscore_shutdown,
2375 .resume = mce_syscore_resume,
2379 * mce_device: Sysfs support
2382 static void mce_cpu_restart(void *data)
2384 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2386 __mcheck_cpu_init_generic();
2387 __mcheck_cpu_init_clear_banks();
2388 __mcheck_cpu_init_timer();
2391 /* Reinit MCEs after user configuration changes */
2392 static void mce_restart(void)
2394 mce_timer_delete_all();
2395 on_each_cpu(mce_cpu_restart, NULL, 1);
2396 mce_schedule_work();
2399 /* Toggle features for corrected errors */
2400 static void mce_disable_cmci(void *data)
2402 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2407 static void mce_enable_ce(void *all)
2409 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2414 __mcheck_cpu_init_timer();
2417 static struct bus_type mce_subsys = {
2418 .name = "machinecheck",
2419 .dev_name = "machinecheck",
2422 DEFINE_PER_CPU(struct device *, mce_device);
2424 static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr)
2426 return container_of(attr, struct mce_bank_dev, attr);
2429 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2432 u8 bank = attr_to_bank(attr)->bank;
2435 if (bank >= per_cpu(mce_num_banks, s->id))
2438 b = &per_cpu(mce_banks_array, s->id)[bank];
2443 return sprintf(buf, "%llx\n", b->ctl);
2446 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2447 const char *buf, size_t size)
2449 u8 bank = attr_to_bank(attr)->bank;
2453 if (kstrtou64(buf, 0, &new) < 0)
2456 if (bank >= per_cpu(mce_num_banks, s->id))
2459 b = &per_cpu(mce_banks_array, s->id)[bank];
2470 static ssize_t set_ignore_ce(struct device *s,
2471 struct device_attribute *attr,
2472 const char *buf, size_t size)
2476 if (kstrtou64(buf, 0, &new) < 0)
2479 mutex_lock(&mce_sysfs_mutex);
2480 if (mca_cfg.ignore_ce ^ !!new) {
2482 /* disable ce features */
2483 mce_timer_delete_all();
2484 on_each_cpu(mce_disable_cmci, NULL, 1);
2485 mca_cfg.ignore_ce = true;
2487 /* enable ce features */
2488 mca_cfg.ignore_ce = false;
2489 on_each_cpu(mce_enable_ce, (void *)1, 1);
2492 mutex_unlock(&mce_sysfs_mutex);
2497 static ssize_t set_cmci_disabled(struct device *s,
2498 struct device_attribute *attr,
2499 const char *buf, size_t size)
2503 if (kstrtou64(buf, 0, &new) < 0)
2506 mutex_lock(&mce_sysfs_mutex);
2507 if (mca_cfg.cmci_disabled ^ !!new) {
2510 on_each_cpu(mce_disable_cmci, NULL, 1);
2511 mca_cfg.cmci_disabled = true;
2514 mca_cfg.cmci_disabled = false;
2515 on_each_cpu(mce_enable_ce, NULL, 1);
2518 mutex_unlock(&mce_sysfs_mutex);
2523 static ssize_t store_int_with_restart(struct device *s,
2524 struct device_attribute *attr,
2525 const char *buf, size_t size)
2527 unsigned long old_check_interval = check_interval;
2528 ssize_t ret = device_store_ulong(s, attr, buf, size);
2530 if (check_interval == old_check_interval)
2533 mutex_lock(&mce_sysfs_mutex);
2535 mutex_unlock(&mce_sysfs_mutex);
2540 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2541 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2542 static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all);
2544 static struct dev_ext_attribute dev_attr_check_interval = {
2545 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2549 static struct dev_ext_attribute dev_attr_ignore_ce = {
2550 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2554 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2555 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2556 &mca_cfg.cmci_disabled
2559 static struct device_attribute *mce_device_attrs[] = {
2560 &dev_attr_check_interval.attr,
2561 #ifdef CONFIG_X86_MCELOG_LEGACY
2564 &dev_attr_monarch_timeout.attr,
2565 &dev_attr_dont_log_ce.attr,
2566 &dev_attr_print_all.attr,
2567 &dev_attr_ignore_ce.attr,
2568 &dev_attr_cmci_disabled.attr,
2572 static cpumask_var_t mce_device_initialized;
2574 static void mce_device_release(struct device *dev)
2579 /* Per CPU device init. All of the CPUs still share the same bank device: */
2580 static int mce_device_create(unsigned int cpu)
2586 if (!mce_available(&boot_cpu_data))
2589 dev = per_cpu(mce_device, cpu);
2593 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2597 dev->bus = &mce_subsys;
2598 dev->release = &mce_device_release;
2600 err = device_register(dev);
2606 for (i = 0; mce_device_attrs[i]; i++) {
2607 err = device_create_file(dev, mce_device_attrs[i]);
2611 for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) {
2612 err = device_create_file(dev, &mce_bank_devs[j].attr);
2616 cpumask_set_cpu(cpu, mce_device_initialized);
2617 per_cpu(mce_device, cpu) = dev;
2622 device_remove_file(dev, &mce_bank_devs[j].attr);
2625 device_remove_file(dev, mce_device_attrs[i]);
2627 device_unregister(dev);
2632 static void mce_device_remove(unsigned int cpu)
2634 struct device *dev = per_cpu(mce_device, cpu);
2637 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2640 for (i = 0; mce_device_attrs[i]; i++)
2641 device_remove_file(dev, mce_device_attrs[i]);
2643 for (i = 0; i < per_cpu(mce_num_banks, cpu); i++)
2644 device_remove_file(dev, &mce_bank_devs[i].attr);
2646 device_unregister(dev);
2647 cpumask_clear_cpu(cpu, mce_device_initialized);
2648 per_cpu(mce_device, cpu) = NULL;
2651 /* Make sure there are no machine checks on offlined CPUs. */
2652 static void mce_disable_cpu(void)
2654 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2657 if (!cpuhp_tasks_frozen)
2660 vendor_disable_error_reporting();
2663 static void mce_reenable_cpu(void)
2665 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2668 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2671 if (!cpuhp_tasks_frozen)
2673 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2674 struct mce_bank *b = &mce_banks[i];
2677 wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl);
2681 static int mce_cpu_dead(unsigned int cpu)
2683 mce_intel_hcpu_update(cpu);
2685 /* intentionally ignoring frozen here */
2686 if (!cpuhp_tasks_frozen)
2691 static int mce_cpu_online(unsigned int cpu)
2693 struct timer_list *t = this_cpu_ptr(&mce_timer);
2696 mce_device_create(cpu);
2698 ret = mce_threshold_create_device(cpu);
2700 mce_device_remove(cpu);
2708 static int mce_cpu_pre_down(unsigned int cpu)
2710 struct timer_list *t = this_cpu_ptr(&mce_timer);
2714 mce_threshold_remove_device(cpu);
2715 mce_device_remove(cpu);
2719 static __init void mce_init_banks(void)
2723 for (i = 0; i < MAX_NR_BANKS; i++) {
2724 struct mce_bank_dev *b = &mce_bank_devs[i];
2725 struct device_attribute *a = &b->attr;
2729 sysfs_attr_init(&a->attr);
2730 a->attr.name = b->attrname;
2731 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2733 a->attr.mode = 0644;
2734 a->show = show_bank;
2735 a->store = set_bank;
2740 * When running on XEN, this initcall is ordered against the XEN mcelog
2743 * device_initcall(xen_late_init_mcelog);
2744 * device_initcall_sync(mcheck_init_device);
2746 static __init int mcheck_init_device(void)
2751 * Check if we have a spare virtual bit. This will only become
2752 * a problem if/when we move beyond 5-level page tables.
2754 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2756 if (!mce_available(&boot_cpu_data)) {
2761 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2768 err = subsys_system_register(&mce_subsys, NULL);
2772 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2778 * Invokes mce_cpu_online() on all CPUs which are online when
2779 * the state is installed.
2781 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2782 mce_cpu_online, mce_cpu_pre_down);
2784 goto err_out_online;
2786 register_syscore_ops(&mce_syscore_ops);
2791 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2794 free_cpumask_var(mce_device_initialized);
2797 pr_err("Unable to init MCE device (rc: %d)\n", err);
2801 device_initcall_sync(mcheck_init_device);
2804 * Old style boot options parsing. Only for compatibility.
2806 static int __init mcheck_disable(char *str)
2808 mca_cfg.disabled = 1;
2811 __setup("nomce", mcheck_disable);
2813 #ifdef CONFIG_DEBUG_FS
2814 struct dentry *mce_get_debugfs_dir(void)
2816 static struct dentry *dmce;
2819 dmce = debugfs_create_dir("mce", NULL);
2824 static void mce_reset(void)
2826 atomic_set(&mce_fake_panicked, 0);
2827 atomic_set(&mce_executing, 0);
2828 atomic_set(&mce_callin, 0);
2829 atomic_set(&global_nwo, 0);
2830 cpumask_setall(&mce_missing_cpus);
2833 static int fake_panic_get(void *data, u64 *val)
2839 static int fake_panic_set(void *data, u64 val)
2846 DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set,
2849 static void __init mcheck_debugfs_init(void)
2851 struct dentry *dmce;
2853 dmce = mce_get_debugfs_dir();
2854 debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL,
2858 static void __init mcheck_debugfs_init(void) { }
2861 static int __init mcheck_late_init(void)
2863 if (mca_cfg.recovery)
2864 enable_copy_mc_fragile();
2866 mcheck_debugfs_init();
2869 * Flush out everything that has been logged during early boot, now that
2870 * everything has been initialized (workqueues, decoders, ...).
2872 mce_schedule_work();
2876 late_initcall(mcheck_late_init);