drm/vc4: hvs: Boost the core clock during modeset

In order to prevent timeouts and stalls in the pipeline, the core clock
needs to be maxed at 500MHz during a modeset on the BCM2711.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/37ed9e0124c5cce005ddc8dafe821d8b0da036ff.1599120059.git-series.maxime@cerno.tech

diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index e4cde1f9224b0f45f2bc6c70de9bae78c241da83..6358f6ca8d56f2928fbc0aed50a1f688f9e058a8 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -320,6 +320,8 @@ struct vc4_hvs {
        void __iomem *regs;
        u32 __iomem *dlist;
 
+       struct clk *core_clk;
+
        /* Memory manager for CRTCs to allocate space in the display
         * list.  Units are dwords.
         */

diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 836d8799d79e04550abc612d5e83623740951fea..abdb43c4cc10dffc601cf8910d77f14acb523ce7 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -19,6 +19,7 @@
  * each CRTC.
  */
 
+#include <linux/clk.h>
 #include <linux/component.h>
 #include <linux/platform_device.h>
 
@@ -540,6 +541,20 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
        hvs->regset.regs = hvs_regs;
        hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
 
+       if (hvs->hvs5) {
+               hvs->core_clk = devm_clk_get(&pdev->dev, NULL);
+               if (IS_ERR(hvs->core_clk)) {
+                       dev_err(&pdev->dev, "Couldn't get core clock\n");
+                       return PTR_ERR(hvs->core_clk);
+               }
+
+               ret = clk_prepare_enable(hvs->core_clk);
+               if (ret) {
+                       dev_err(&pdev->dev, "Couldn't enable the core clock\n");
+                       return ret;
+               }
+       }
+
        if (!hvs->hvs5)
                hvs->dlist = hvs->regs + SCALER_DLIST_START;
        else
@@ -624,6 +639,7 @@ static void vc4_hvs_unbind(struct device *dev, struct device *master,
 {
        struct drm_device *drm = dev_get_drvdata(master);
        struct vc4_dev *vc4 = drm->dev_private;
+       struct vc4_hvs *hvs = vc4->hvs;
 
        if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter))
                drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
@@ -631,6 +647,8 @@ static void vc4_hvs_unbind(struct device *dev, struct device *master,
        drm_mm_takedown(&vc4->hvs->dlist_mm);
        drm_mm_takedown(&vc4->hvs->lbm_mm);
 
+       clk_disable_unprepare(hvs->core_clk);
+
        vc4->hvs = NULL;
 }
 

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 08318e69061be37c7995e311289eb58d7c9f1ee5..210cc2408087757dc1e8045ce77f8f5df4a05d92 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -11,6 +11,8 @@
  * crtc, HDMI encoder).
  */
 
+#include <linux/clk.h>
+
 #include <drm/drm_atomic.h>
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
@@ -149,6 +151,7 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
 {
        struct drm_device *dev = state->dev;
        struct vc4_dev *vc4 = to_vc4_dev(dev);
+       struct vc4_hvs *hvs = vc4->hvs;
        struct vc4_crtc *vc4_crtc;
        int i;
 
@@ -160,6 +163,9 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
                vc4_hvs_mask_underrun(dev, vc4_crtc->channel);
        }
 
+       if (vc4->hvs->hvs5)
+               clk_set_min_rate(hvs->core_clk, 500000000);
+
        drm_atomic_helper_wait_for_fences(dev, state, false);
 
        drm_atomic_helper_wait_for_dependencies(state);
@@ -182,6 +188,9 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
 
        drm_atomic_helper_commit_cleanup_done(state);
 
+       if (vc4->hvs->hvs5)
+               clk_set_min_rate(hvs->core_clk, 0);
+
        drm_atomic_state_put(state);
 
        up(&vc4->async_modeset);