#define TURING_A /* cl9097.h */ 0x0000c597
+#define AMPERE_B /* cl9097.h */ 0x0000c797
+
#define NV74_BSP 0x000074b0
#define GT212_MSVLD 0x000085b1
#define PASCAL_COMPUTE_B 0x0000c1c0
#define VOLTA_COMPUTE_A 0x0000c3c0
#define TURING_COMPUTE_A 0x0000c5c0
+#define AMPERE_COMPUTE_B 0x0000c7c0
#define NV74_CIPHER 0x000074c1
#endif
int gp10b_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gv100_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int tu102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
+int ga102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
#endif
#define NVKM_ACR_LSF_DMACTL_REQ_CTX 0x00000004
#define NVKM_ACR_LSF_FORCE_PRIV_LOAD 0x00000008
u32 flags;
+ u32 bl_entry;
u32 bld_size;
void (*bld_write)(struct nvkm_acr *, u32 bld, struct nvkm_acr_lsfw *);
void (*bld_patch)(struct nvkm_acr *, u32 bld, s64 adjust);
nvkm_acr_lsfw_load_bl_inst_data_sig(struct nvkm_subdev *, struct nvkm_falcon *,
enum nvkm_acr_lsf_id, const char *path,
int ver, const struct nvkm_acr_lsf_func *);
+
+int
+nvkm_acr_lsfw_load_bl_sig_net(struct nvkm_subdev *, struct nvkm_falcon *,
+ enum nvkm_acr_lsf_id, const char *path,
+ int ver, const struct nvkm_acr_lsf_func *,
+ const void *, u32, const void *, u32);
#endif
.disp = { 0x00000001, ga102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, ga102_fifo_new },
+ .gr = { 0x00000001, ga102_gr_new },
.nvdec = { 0x00000001, ga102_nvdec_new },
.sec2 = { 0x00000001, ga102_sec2_new },
};
.disp = { 0x00000001, ga102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, ga102_fifo_new },
+ .gr = { 0x00000001, ga102_gr_new },
.nvdec = { 0x00000001, ga102_nvdec_new },
.sec2 = { 0x00000001, ga102_sec2_new },
};
.disp = { 0x00000001, ga102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, ga102_fifo_new },
+ .gr = { 0x00000001, ga102_gr_new },
.nvdec = { 0x00000001, ga102_nvdec_new },
.sec2 = { 0x00000001, ga102_sec2_new },
};
.disp = { 0x00000001, ga102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, ga102_fifo_new },
+ .gr = { 0x00000001, ga102_gr_new },
.nvdec = { 0x00000001, ga102_nvdec_new },
.sec2 = { 0x00000001, ga102_sec2_new },
};
.disp = { 0x00000001, ga102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, ga102_fifo_new },
+ .gr = { 0x00000001, ga102_gr_new },
.nvdec = { 0x00000001, ga102_nvdec_new },
.sec2 = { 0x00000001, ga102_sec2_new },
};
nvkm-y += nvkm/engine/gr/gp10b.o
nvkm-y += nvkm/engine/gr/gv100.o
nvkm-y += nvkm/engine/gr/tu102.o
+nvkm-y += nvkm/engine/gr/ga102.o
nvkm-y += nvkm/engine/gr/ctxnv40.o
nvkm-y += nvkm/engine/gr/ctxnv50.o
nvkm-y += nvkm/engine/gr/ctxgp107.o
nvkm-y += nvkm/engine/gr/ctxgv100.o
nvkm-y += nvkm/engine/gr/ctxtu102.o
+nvkm-y += nvkm/engine/gr/ctxga102.o
--- /dev/null
+/*
+ * Copyright 2019 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "ctxgf100.h"
+
+static void
+ga102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
+{
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+
+ tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc);
+
+ nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
+}
+
+static void
+ga102_grctx_generate_unkn(struct gf100_gr *gr)
+{
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+
+ nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);
+ nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004);
+}
+
+static void
+ga102_grctx_generate_r419ea8(struct gf100_gr *gr)
+{
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+
+ nvkm_wr32(device, 0x419ea8, nvkm_rd32(device, 0x504728) | 0x08000000);
+}
+
+const struct gf100_grctx_func
+ga102_grctx = {
+ .main = gf100_grctx_generate_main,
+ .unkn = ga102_grctx_generate_unkn,
+ .bundle = gm107_grctx_generate_bundle,
+ .bundle_size = 0x3000,
+ .bundle_min_gpm_fifo_depth = 0x180,
+ .bundle_token_limit = 0x1140,
+ .pagepool = gp100_grctx_generate_pagepool,
+ .pagepool_size = 0x20000,
+ .attrib_cb_size = gp102_grctx_generate_attrib_cb_size,
+ .attrib_cb = gv100_grctx_generate_attrib_cb,
+ .attrib = gv100_grctx_generate_attrib,
+ .attrib_nr_max = 0x800,
+ .attrib_nr = 0x4a1,
+ .alpha_nr_max = 0xc00,
+ .alpha_nr = 0x800,
+ .unknown_size = 0x80000,
+ .unknown = tu102_grctx_generate_unknown,
+ .gfxp_nr = 0xd28,
+ .sm_id = ga102_grctx_generate_sm_id,
+ .skip_pd_num_tpc_per_gpc = true,
+ .rop_mapping = gv100_grctx_generate_rop_mapping,
+ .r406500 = gm200_grctx_generate_r406500,
+ .r400088 = gv100_grctx_generate_r400088,
+ .r419ea8 = ga102_grctx_generate_r419ea8,
+};
if (gr->func->init_419bd8)
gr->func->init_419bd8(gr);
+ if (grctx->r419ea8)
+ grctx->r419ea8(gr);
gf100_gr_wait_idle(gr);
void (*r419a3c)(struct gf100_gr *);
void (*r408840)(struct gf100_gr *);
void (*r419c0c)(struct gf100_gr *);
+ void (*r419ea8)(struct gf100_gr *);
};
extern const struct gf100_grctx_func gf100_grctx;
void tu102_grctx_generate_unknown(struct gf100_gr_chan *, u64, u32);
+extern const struct gf100_grctx_func ga102_grctx;
+
/* context init value lists */
extern const struct gf100_gr_pack gf100_grctx_pack_icmd[];
--- /dev/null
+/*
+ * Copyright 2019 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "gf100.h"
+#include "ctxgf100.h"
+
+#include <core/firmware.h>
+#include <subdev/acr.h>
+#include <subdev/timer.h>
+#include <subdev/vfn.h>
+
+#include <nvfw/flcn.h>
+
+#include <nvif/class.h>
+
+static void
+ga102_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
+{
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+ u32 invalid[] = { 0, 0, 0, 0 }, *color;
+
+ if (gr->zbc_color[zbc].format)
+ color = gr->zbc_color[zbc].l2;
+ else
+ color = invalid;
+
+ nvkm_mask(device, 0x41bcb4, 0x0000001f, zbc);
+ nvkm_wr32(device, 0x41bcec, color[0]);
+ nvkm_wr32(device, 0x41bcf0, color[1]);
+ nvkm_wr32(device, 0x41bcf4, color[2]);
+ nvkm_wr32(device, 0x41bcf8, color[3]);
+}
+
+static const struct gf100_gr_func_zbc
+ga102_gr_zbc = {
+ .clear_color = ga102_gr_zbc_clear_color,
+ .clear_depth = gp100_gr_zbc_clear_depth,
+ .stencil_get = gp102_gr_zbc_stencil_get,
+ .clear_stencil = gp102_gr_zbc_clear_stencil,
+};
+
+static void
+ga102_gr_gpccs_reset(struct gf100_gr *gr)
+{
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+
+ nvkm_wr32(device, 0x41a610, 0x00000000);
+ nvkm_msec(device, 1, NVKM_DELAY);
+ nvkm_wr32(device, 0x41a610, 0x00000001);
+}
+
+static const struct nvkm_acr_lsf_func
+ga102_gr_gpccs_acr = {
+ .flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
+ .bl_entry = 0x3400,
+ .bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
+ .bld_write = gp108_gr_acr_bld_write,
+ .bld_patch = gp108_gr_acr_bld_patch,
+};
+
+static void
+ga102_gr_fecs_reset(struct gf100_gr *gr)
+{
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+
+ nvkm_wr32(device, 0x409614, 0x00000010);
+ nvkm_wr32(device, 0x41a614, 0x00000020);
+ nvkm_usec(device, 10, NVKM_DELAY);
+ nvkm_wr32(device, 0x409614, 0x00000110);
+ nvkm_wr32(device, 0x41a614, 0x00000a20);
+ nvkm_usec(device, 10, NVKM_DELAY);
+ nvkm_rd32(device, 0x409614);
+ nvkm_rd32(device, 0x41a614);
+}
+
+static const struct nvkm_acr_lsf_func
+ga102_gr_fecs_acr = {
+ .bl_entry = 0x7e00,
+ .bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
+ .bld_write = gp108_gr_acr_bld_write,
+ .bld_patch = gp108_gr_acr_bld_patch,
+};
+
+static void
+ga102_gr_init_rop_exceptions(struct gf100_gr *gr)
+{
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+
+ nvkm_wr32(device, 0x41bcbc, 0x40000000);
+ nvkm_wr32(device, 0x41bc38, 0x40000000);
+ nvkm_wr32(device, 0x41ac94, nvkm_rd32(device, 0x502c94));
+}
+
+static void
+ga102_gr_init_40a790(struct gf100_gr *gr)
+{
+ nvkm_wr32(gr->base.engine.subdev.device, 0x40a790, 0xc0000000);
+}
+
+static void
+ga102_gr_init_gpc_mmu(struct gf100_gr *gr)
+{
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+
+ nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff);
+ nvkm_wr32(device, 0x418894, 0x00000000);
+
+ nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
+ nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
+ nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
+}
+
+static struct nvkm_intr *
+ga102_gr_oneinit_intr(struct gf100_gr *gr, enum nvkm_intr_type *pvector)
+{
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+
+ *pvector = nvkm_rd32(device, 0x400154) & 0x00000fff;
+ return &device->vfn->intr;
+}
+
+static const struct gf100_gr_func
+ga102_gr = {
+ .oneinit_intr = ga102_gr_oneinit_intr,
+ .oneinit_tiles = gm200_gr_oneinit_tiles,
+ .oneinit_sm_id = gv100_gr_oneinit_sm_id,
+ .init = gf100_gr_init,
+ .init_419bd8 = gv100_gr_init_419bd8,
+ .init_gpc_mmu = ga102_gr_init_gpc_mmu,
+ .init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
+ .init_zcull = tu102_gr_init_zcull,
+ .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
+ .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
+ .init_fs = tu102_gr_init_fs,
+ .init_fecs_exceptions = tu102_gr_init_fecs_exceptions,
+ .init_40a790 = ga102_gr_init_40a790,
+ .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
+ .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
+ .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
+ .init_504430 = gv100_gr_init_504430,
+ .init_shader_exceptions = gv100_gr_init_shader_exceptions,
+ .init_rop_exceptions = ga102_gr_init_rop_exceptions,
+ .init_4188a4 = gv100_gr_init_4188a4,
+ .trap_mp = gv100_gr_trap_mp,
+ .fecs.reset = ga102_gr_fecs_reset,
+ .gpccs.reset = ga102_gr_gpccs_reset,
+ .rops = gm200_gr_rops,
+ .gpc_nr = 7,
+ .tpc_nr = 6,
+ .ppc_nr = 3,
+ .grctx = &ga102_grctx,
+ .zbc = &ga102_gr_zbc,
+ .sclass = {
+ { -1, -1, FERMI_TWOD_A },
+ { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
+ { -1, -1, AMPERE_B, &gf100_fermi },
+ { -1, -1, AMPERE_COMPUTE_B },
+ {}
+ }
+};
+
+MODULE_FIRMWARE("nvidia/ga102/gr/fecs_bl.bin");
+MODULE_FIRMWARE("nvidia/ga102/gr/fecs_sig.bin");
+MODULE_FIRMWARE("nvidia/ga102/gr/gpccs_bl.bin");
+MODULE_FIRMWARE("nvidia/ga102/gr/gpccs_sig.bin");
+MODULE_FIRMWARE("nvidia/ga102/gr/NET_img.bin");
+
+MODULE_FIRMWARE("nvidia/ga103/gr/fecs_bl.bin");
+MODULE_FIRMWARE("nvidia/ga103/gr/fecs_sig.bin");
+MODULE_FIRMWARE("nvidia/ga103/gr/gpccs_bl.bin");
+MODULE_FIRMWARE("nvidia/ga103/gr/gpccs_sig.bin");
+MODULE_FIRMWARE("nvidia/ga103/gr/NET_img.bin");
+
+MODULE_FIRMWARE("nvidia/ga104/gr/fecs_bl.bin");
+MODULE_FIRMWARE("nvidia/ga104/gr/fecs_sig.bin");
+MODULE_FIRMWARE("nvidia/ga104/gr/gpccs_bl.bin");
+MODULE_FIRMWARE("nvidia/ga104/gr/gpccs_sig.bin");
+MODULE_FIRMWARE("nvidia/ga104/gr/NET_img.bin");
+
+MODULE_FIRMWARE("nvidia/ga106/gr/fecs_bl.bin");
+MODULE_FIRMWARE("nvidia/ga106/gr/fecs_sig.bin");
+MODULE_FIRMWARE("nvidia/ga106/gr/gpccs_bl.bin");
+MODULE_FIRMWARE("nvidia/ga106/gr/gpccs_sig.bin");
+MODULE_FIRMWARE("nvidia/ga106/gr/NET_img.bin");
+
+MODULE_FIRMWARE("nvidia/ga107/gr/fecs_bl.bin");
+MODULE_FIRMWARE("nvidia/ga107/gr/fecs_sig.bin");
+MODULE_FIRMWARE("nvidia/ga107/gr/gpccs_bl.bin");
+MODULE_FIRMWARE("nvidia/ga107/gr/gpccs_sig.bin");
+MODULE_FIRMWARE("nvidia/ga107/gr/NET_img.bin");
+
+struct netlist_region {
+ u32 region_id;
+ u32 data_size;
+ u32 data_offset;
+};
+
+struct netlist_image_header {
+ u32 version;
+ u32 regions;
+};
+
+struct netlist_image {
+ struct netlist_image_header header;
+ struct netlist_region regions[];
+};
+
+struct netlist_av64 {
+ u32 addr;
+ u32 data_hi;
+ u32 data_lo;
+};
+
+static int
+ga102_gr_av64_to_init(struct nvkm_blob *blob, struct gf100_gr_pack **ppack)
+{
+ struct gf100_gr_init *init;
+ struct gf100_gr_pack *pack;
+ int nent;
+ int i;
+
+ nent = (blob->size / sizeof(struct netlist_av64));
+ pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
+ if (!pack)
+ return -ENOMEM;
+
+ init = (void *)(pack + 2);
+ pack[0].init = init;
+ pack[0].type = 64;
+
+ for (i = 0; i < nent; i++) {
+ struct gf100_gr_init *ent = &init[i];
+ struct netlist_av64 *av = &((struct netlist_av64 *)blob->data)[i];
+
+ ent->addr = av->addr;
+ ent->data = ((u64)av->data_hi << 32) | av->data_lo;
+ ent->count = 1;
+ ent->pitch = 1;
+ }
+
+ *ppack = pack;
+ return 0;
+}
+
+static int
+ga102_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
+{
+ struct nvkm_subdev *subdev = &gr->base.engine.subdev;
+ const struct firmware *fw;
+ const struct netlist_image *net;
+ const struct netlist_region *fecs_inst = NULL;
+ const struct netlist_region *fecs_data = NULL;
+ const struct netlist_region *gpccs_inst = NULL;
+ const struct netlist_region *gpccs_data = NULL;
+ int ret, i;
+
+ ret = nvkm_firmware_get(subdev, "gr/NET_img", 0, &fw);
+ if (ret)
+ return ret;
+
+ net = (const void *)fw->data;
+ nvkm_debug(subdev, "netlist version %d, %d regions\n",
+ net->header.version, net->header.regions);
+
+ for (i = 0; i < net->header.regions; i++) {
+ const struct netlist_region *reg = &net->regions[i];
+ struct nvkm_blob blob = {
+ .data = (void *)fw->data + reg->data_offset,
+ .size = reg->data_size,
+ };
+
+ nvkm_debug(subdev, "\t%2d: %08x %08x\n",
+ reg->region_id, reg->data_offset, reg->data_size);
+
+ switch (reg->region_id) {
+ case 0: fecs_data = reg; break;
+ case 1: fecs_inst = reg; break;
+ case 2: gpccs_data = reg; break;
+ case 3: gpccs_inst = reg; break;
+ case 4: gk20a_gr_av_to_init(&blob, &gr->bundle); break;
+ case 5: gk20a_gr_aiv_to_init(&blob, &gr->sw_ctx); break;
+ case 7: gk20a_gr_av_to_method(&blob, &gr->method); break;
+ case 28: tu102_gr_av_to_init_veid(&blob, &gr->bundle_veid); break;
+ case 34: ga102_gr_av64_to_init(&blob, &gr->bundle64); break;
+ case 48: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx1); break;
+ case 49: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx2); break;
+ case 50: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx3); break;
+ case 51: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx4); break;
+ default:
+ break;
+ }
+ }
+
+ ret = nvkm_acr_lsfw_load_bl_sig_net(subdev, &gr->fecs.falcon, NVKM_ACR_LSF_FECS,
+ "gr/fecs_", ver, fwif->fecs,
+ fw->data + fecs_inst->data_offset,
+ fecs_inst->data_size,
+ fw->data + fecs_data->data_offset,
+ fecs_data->data_size);
+ if (ret)
+ return ret;
+
+ ret = nvkm_acr_lsfw_load_bl_sig_net(subdev, &gr->gpccs.falcon, NVKM_ACR_LSF_GPCCS,
+ "gr/gpccs_", ver, fwif->gpccs,
+ fw->data + gpccs_inst->data_offset,
+ gpccs_inst->data_size,
+ fw->data + gpccs_data->data_offset,
+ gpccs_data->data_size);
+ if (ret)
+ return ret;
+
+ gr->firmware = true;
+
+ nvkm_firmware_put(fw);
+ return 0;
+}
+
+static const struct gf100_gr_fwif
+ga102_gr_fwif[] = {
+ { 0, ga102_gr_load, &ga102_gr, &ga102_gr_fecs_acr, &ga102_gr_gpccs_acr },
+ { -1, gm200_gr_nofw },
+ {}
+};
+
+int
+ga102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
+{
+ return gf100_gr_new_(ga102_gr_fwif, device, type, inst, pgr);
+}
enum nvkm_intr_type intr_type = NVKM_INTR_SUBDEV;
int ret, i, j;
+ if (gr->func->oneinit_intr)
+ intr = gr->func->oneinit_intr(gr, &intr_type);
+
ret = nvkm_inth_add(intr, intr_type, NVKM_INTR_PRIO_NORMAL, &gr->base.engine.subdev,
gf100_gr_intr, &gr->base.engine.subdev.inth);
if (ret)
vfree(gr->method);
vfree(gr->sw_ctx);
vfree(gr->sw_nonctx);
+ vfree(gr->sw_nonctx1);
+ vfree(gr->sw_nonctx2);
+ vfree(gr->sw_nonctx3);
+ vfree(gr->sw_nonctx4);
return gr;
}
subdev->func->fini(subdev, false);
nvkm_mc_disable(device, subdev->type, subdev->inst);
+ if (gr->func->gpccs.reset)
+ gr->func->gpccs.reset(gr);
nvkm_mc_enable(device, subdev->type, subdev->inst);
return subdev->func->init(subdev);
gr->func->init_gpc_mmu(gr);
- if (gr->sw_nonctx)
+ if (gr->sw_nonctx1) {
+ gf100_gr_mmio(gr, gr->sw_nonctx1);
+ gf100_gr_mmio(gr, gr->sw_nonctx2);
+ gf100_gr_mmio(gr, gr->sw_nonctx3);
+ gf100_gr_mmio(gr, gr->sw_nonctx4);
+ } else
+ if (gr->sw_nonctx) {
gf100_gr_mmio(gr, gr->sw_nonctx);
- else
+ } else {
gf100_gr_mmio(gr, gr->func->mmio);
+ }
gf100_gr_wait_idle(gr);
nvkm_wr32(device, 0x400124, 0x00000002);
gr->func->init_fecs_exceptions(gr);
+
+ if (gr->func->init_40a790)
+ gr->func->init_40a790(gr);
+
if (gr->func->init_ds_hww_esr_2)
gr->func->init_ds_hww_esr_2(gr);
* using hardcoded arrays. To be allocated with vzalloc().
*/
struct gf100_gr_pack *sw_nonctx;
+ struct gf100_gr_pack *sw_nonctx1;
+ struct gf100_gr_pack *sw_nonctx2;
+ struct gf100_gr_pack *sw_nonctx3;
+ struct gf100_gr_pack *sw_nonctx4;
struct gf100_gr_pack *sw_ctx;
struct gf100_gr_pack *bundle;
struct gf100_gr_pack *bundle_veid;
};
struct gf100_gr_func {
+ struct nvkm_intr *(*oneinit_intr)(struct gf100_gr *, enum nvkm_intr_type *);
void (*oneinit_tiles)(struct gf100_gr *);
int (*oneinit_sm_id)(struct gf100_gr *);
int (*init)(struct gf100_gr *);
void (*init_swdx_pes_mask)(struct gf100_gr *);
void (*init_fs)(struct gf100_gr *);
void (*init_fecs_exceptions)(struct gf100_gr *);
+ void (*init_40a790)(struct gf100_gr *);
void (*init_ds_hww_esr_2)(struct gf100_gr *);
void (*init_40601c)(struct gf100_gr *);
void (*init_sked_hww_esr)(struct gf100_gr *);
} fecs;
struct {
struct gf100_gr_ucode *ucode;
+ void (*reset)(struct gf100_gr *);
} gpccs;
int (*rops)(struct gf100_gr *);
int gpc_nr;
void gp102_gr_init_swdx_pes_mask(struct gf100_gr *);
extern const struct gf100_gr_func_zbc gp102_gr_zbc;
+int gp102_gr_zbc_stencil_get(struct gf100_gr *, int, const u32, const u32);
+void gp102_gr_zbc_clear_stencil(struct gf100_gr *, int);
extern const struct gf100_gr_func gp107_gr;
void gv100_gr_trap_mp(struct gf100_gr *, int, int);
int tu102_gr_av_to_init_veid(struct nvkm_blob *, struct gf100_gr_pack **);
+void tu102_gr_init_zcull(struct gf100_gr *);
+void tu102_gr_init_fs(struct gf100_gr *);
+void tu102_gr_init_fecs_exceptions(struct gf100_gr *);
#define gf100_gr_chan(p) container_of((p), struct gf100_gr_chan, object)
#include <core/object.h>
extern const struct nvkm_acr_lsf_func gp108_gr_gpccs_acr;
extern const struct nvkm_acr_lsf_func gp108_gr_fecs_acr;
+void gp108_gr_acr_bld_write(struct nvkm_acr *, u32, struct nvkm_acr_lsfw *);
+void gp108_gr_acr_bld_patch(struct nvkm_acr *, u32, s64);
int gf100_gr_new_(const struct gf100_gr_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_gr **);
#include <nvif/class.h>
-static void
+void
gp102_gr_zbc_clear_stencil(struct gf100_gr *gr, int zbc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
gr->zbc_stencil[zbc].format << ((znum % 4) * 7));
}
-static int
+int
gp102_gr_zbc_stencil_get(struct gf100_gr *gr, int format,
const u32 ds, const u32 l2)
{
#include <nvfw/flcn.h>
-static void
+void
gp108_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
{
struct flcn_bl_dmem_desc_v2 hdr;
flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr);
}
-static void
+void
gp108_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
struct nvkm_acr_lsfw *lsfw)
{
#include <nvif/class.h>
-static void
+void
tu102_gr_init_fecs_exceptions(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006e0003);
}
-static void
+void
tu102_gr_init_fs(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
gf100_gr_init_num_tpc_per_gpc(gr, true, true);
}
-static void
+void
tu102_gr_init_zcull(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_firmware_put(bl);
return ret;
}
+
+int
+nvkm_acr_lsfw_load_bl_sig_net(struct nvkm_subdev *subdev,
+ struct nvkm_falcon *falcon,
+ enum nvkm_acr_lsf_id id,
+ const char *path, int ver,
+ const struct nvkm_acr_lsf_func *func,
+ const void *inst_data, u32 inst_size,
+ const void *data_data, u32 data_size)
+{
+ struct nvkm_acr *acr = subdev->device->acr;
+ struct nvkm_acr_lsfw *lsfw;
+ const struct firmware _inst = { .data = inst_data, .size = inst_size };
+ const struct firmware _data = { .data = data_data, .size = data_size };
+ const struct firmware *bl = NULL, *inst = &_inst, *data = &_data;
+ const struct {
+ int bin_magic;
+ int bin_version;
+ int bin_size;
+ int header_offset;
+ int header_size;
+ } *hdr;
+ u32 *bldata;
+ int ret;
+
+ if (IS_ERR((lsfw = nvkm_acr_lsfw_add(func, acr, falcon, id))))
+ return PTR_ERR(lsfw);
+
+ ret = nvkm_firmware_load_name(subdev, path, "bl", ver, &bl);
+ if (ret)
+ goto done;
+
+ hdr = (const void *)bl->data;
+ bldata = (void *)(bl->data + hdr->header_offset);
+
+ ret = nvkm_firmware_load_name(subdev, path, "sig", ver, &lsfw->sig);
+ if (ret)
+ goto done;
+
+ lsfw->bootloader_size = ALIGN(hdr->header_size, 256);
+ lsfw->bootloader_imem_offset = func->bl_entry;
+
+ lsfw->app_start_offset = lsfw->bootloader_size;
+ lsfw->app_imem_entry = 0;
+ lsfw->app_resident_code_offset = 0;
+ lsfw->app_resident_code_size = ALIGN(inst->size, 256);
+ lsfw->app_resident_data_offset = lsfw->app_resident_code_size;
+ lsfw->app_resident_data_size = ALIGN(data->size, 256);
+ lsfw->app_imem_offset = 0;
+ lsfw->app_dmem_offset = 0;
+ lsfw->app_size = lsfw->app_resident_code_size + lsfw->app_resident_data_size;
+
+ lsfw->img.size = lsfw->bootloader_size + lsfw->app_size;
+ if (!(lsfw->img.data = kzalloc(lsfw->img.size, GFP_KERNEL))) {
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ memcpy(lsfw->img.data, bldata, lsfw->bootloader_size);
+ memcpy(lsfw->img.data + lsfw->app_start_offset +
+ lsfw->app_resident_code_offset, inst->data, inst->size);
+ memcpy(lsfw->img.data + lsfw->app_start_offset +
+ lsfw->app_resident_data_offset, data->data, data->size);
+
+ lsfw->ucode_size = ALIGN(lsfw->app_resident_data_offset, 256) +
+ lsfw->bootloader_size;
+ lsfw->data_size = lsfw->app_size + lsfw->bootloader_size -
+ lsfw->ucode_size;
+
+done:
+ if (ret)
+ nvkm_acr_lsfw_del(lsfw);
+ nvkm_firmware_put(bl);
+ return ret;
+}
git.samba.org / sfrench / cifs-2.6.git / commitdiff