Merge tag 'v5.16' into rdma.git for-next

To resolve minor conflict in:
        drivers/infiniband/hw/mlx5/mlx5_ib.h

By merging both hunks.

Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

diff --cc drivers/infiniband/hw/hns/hns_roce_hw_v2.c
Simple merge

diff --cc drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index e9a73c34389bd846c65e4aaff129eff81c1c910d,35c61da7ba156be04bb76d7cb041cc99eba0161b..12be85f0986ea6d726dd4110139eae7b14bd0d49
--- 1/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
--- 2/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@@ -1427,9 -1441,17 +1427,17 @@@ struct hns_roce_v2_priv 
  struct hns_roce_dip {
        u8 dgid[GID_LEN_V2];
        u32 dip_idx;
 -      struct list_head node;  /* all dips are on a list */
 +      struct list_head node; /* all dips are on a list */
  };
  
+ /* only for RNR timeout issue of HIP08 */
+ #define HNS_ROCE_CLOCK_ADJUST 1000
+ #define HNS_ROCE_MAX_CQ_PERIOD 65
+ #define HNS_ROCE_MAX_EQ_PERIOD 65
+ #define HNS_ROCE_RNR_TIMER_10NS 1
+ #define HNS_ROCE_1US_CFG 999
+ #define HNS_ROCE_1NS_CFG 0
+ 
  #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM        0x0
  #define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0
  #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM        0x0

diff --cc drivers/infiniband/hw/mlx5/mlx5_ib.h
index 35d27f455eb91f9e4b9e695c42df576dc3b09a80,e636e954f6bf2a30061ed41d2dcaa4a91557e9e7..cbc20e400be0deac65faff0ecdcdbb71d394890e
--- 1/drivers/infiniband/hw/mlx5/mlx5_ib.h
--- 2/drivers/infiniband/hw/mlx5/mlx5_ib.h
+++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h
@@@ -665,8 -664,9 +665,9 @@@ struct mlx5_ib_mr 
  
        /* User MR data */
        struct mlx5_cache_ent *cache_ent;
 +      /* Everything after cache_ent is zero'd when MR allocated */
+       struct ib_umem *umem;
  
 -      /* This is zero'd when the MR is allocated */
        union {
                /* Used only while the MR is in the cache */
                struct {

diff --cc drivers/infiniband/sw/rxe/rxe_mr.c
Simple merge