MIPS: reduce print level for cache information

Default printk log level is KERN_WARNING. This makes automatic log
parsing problematic, since we get false positive alarms on not critical
information.

Set all not critical cache related information to KERN_INFO, the same level
as used on most kernel drivers.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 8064821e9805e37cb6de94086ebc0cb3eef18839..4baf965e6fe8c43b8010287d09e03ddcc3c99bbf 100644 (file)
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -237,17 +237,17 @@ static void probe_octeon(void)
        c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
 
        if (smp_processor_id() == 0) {
-               pr_notice("Primary instruction cache %ldkB, %s, %d way, "
-                         "%d sets, linesize %d bytes.\n",
-                         icache_size >> 10,
-                         cpu_has_vtag_icache ?
+               pr_info("Primary instruction cache %ldkB, %s, %d way, "
+                       "%d sets, linesize %d bytes.\n",
+                       icache_size >> 10,
+                       cpu_has_vtag_icache ?
                                "virtually tagged" : "physically tagged",
-                         c->icache.ways, c->icache.sets, c->icache.linesz);
+                       c->icache.ways, c->icache.sets, c->icache.linesz);
 
-               pr_notice("Primary data cache %ldkB, %d-way, %d sets, "
-                         "linesize %d bytes.\n",
-                         dcache_size >> 10, c->dcache.ways,
-                         c->dcache.sets, c->dcache.linesz);
+               pr_info("Primary data cache %ldkB, %d-way, %d sets, "
+                       "linesize %d bytes.\n",
+                       dcache_size >> 10, c->dcache.ways,
+                       c->dcache.sets, c->dcache.linesz);
        }
 }
 

diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 15bb8cf5982867618f3d38e2fa188d425fc37d55..780dd2a567c1e22302e8bb0cbff234262e2897c9 100644 (file)
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -316,9 +316,9 @@ void r3k_cache_init(void)
        _dma_cache_wback = r3k_dma_cache_wback_inv;
        _dma_cache_inv = r3k_dma_cache_wback_inv;
 
-       printk("Primary instruction cache %ldkB, linesize %ld bytes.\n",
+       pr_info("Primary instruction cache %ldkB, linesize %ld bytes.\n",
                icache_size >> 10, icache_lsize);
-       printk("Primary data cache %ldkB, linesize %ld bytes.\n",
+       pr_info("Primary data cache %ldkB, linesize %ld bytes.\n",
                dcache_size >> 10, dcache_lsize);
 
        build_clear_page();

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 5f3d0103b95da61ee19a56f06283840ae0ef7e30..3472f6deaf923a35f6b2482fe91103de40063e78 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1467,17 +1467,17 @@ static void probe_pcache(void)
                c->icache.ways = 1;
        }
 
-       printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
-              icache_size >> 10,
-              c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
-              way_string[c->icache.ways], c->icache.linesz);
-
-       printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
-              dcache_size >> 10, way_string[c->dcache.ways],
-              (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
-              (c->dcache.flags & MIPS_CACHE_ALIASES) ?
+       pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
+               icache_size >> 10,
+               c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
+               way_string[c->icache.ways], c->icache.linesz);
+
+       pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
+               dcache_size >> 10, way_string[c->dcache.ways],
+               (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
+               (c->dcache.flags & MIPS_CACHE_ALIASES) ?
                        "cache aliases" : "no aliases",
-              c->dcache.linesz);
+               c->dcache.linesz);
 }
 
 static void probe_vcache(void)

diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 686867270627c76e79703ca896b42b9bd680d330..2d479cc7e66b51e526e5aa3c1a427fd10f65681d 100644 (file)
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -410,9 +410,9 @@ void tx39_cache_init(void)
        current_cpu_data.icache.waybit = 0;
        current_cpu_data.dcache.waybit = 0;
 
-       printk("Primary instruction cache %ldkB, linesize %d bytes\n",
+       pr_info("Primary instruction cache %ldkB, linesize %d bytes\n",
                icache_size >> 10, current_cpu_data.icache.linesz);
-       printk("Primary data cache %ldkB, linesize %d bytes\n",
+       pr_info("Primary data cache %ldkB, linesize %d bytes\n",
                dcache_size >> 10, current_cpu_data.dcache.linesz);
 
        build_clear_page();