x86/ioapic: Correct the PCI/ISA trigger type selection
authorThomas Gleixner <tglx@linutronix.de>
Tue, 10 Nov 2020 14:34:32 +0000 (15:34 +0100)
committerThomas Gleixner <tglx@linutronix.de>
Tue, 10 Nov 2020 17:43:22 +0000 (18:43 +0100)
PCI's default trigger type is level and ISA's is edge. The recent
refactoring made it the other way round, which went unnoticed as it seems
only to cause havoc on some AMD systems.

Make the comment and code do the right thing again.

Fixes: a27dca645d2c ("x86/io_apic: Cleanup trigger/polarity helpers")
Reported-by: Tom Lendacky <thomas.lendacky@amd.com>
Reported-by: Borislav Petkov <bp@alien8.de>
Reported-by: Qian Cai <cai@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Tom Lendacky <thomas.lendacky@amd.com>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Link: https://lore.kernel.org/r/87d00lgu13.fsf@nanos.tec.linutronix.de
arch/x86/kernel/apic/io_apic.c

index 0602c9533d17aeaf2c73f7aa5da424d7d0f5beed..089e755eadf60939f8f90cc75acebc50d2008d90 100644 (file)
@@ -809,9 +809,9 @@ static bool irq_is_level(int idx)
        case MP_IRQTRIG_DEFAULT:
                /*
                 * Conforms to spec, ie. bus-type dependent trigger
-                * mode. PCI defaults to egde, ISA to level.
+                * mode. PCI defaults to level, ISA to edge.
                 */
-               level = test_bit(bus, mp_bus_not_pci);
+               level = !test_bit(bus, mp_bus_not_pci);
                /* Take EISA into account */
                return eisa_irq_is_level(idx, bus, level);
        case MP_IRQTRIG_EDGE: