arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific

We can use CPU specific pmu configuration to expose the appropriate
CPU specific events rather than just the basic generic pmuv3 perf
events.

Reported-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Tero Kristo <kristo@kernel.org>
Link: https://lore.kernel.org/r/20210120195145.32259-1-nm@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index d84c0bc05023373e7cbebdd41c2c21655be79bb0..a9fc1af03f27f77bf1c78d5295a08415ce8bade4 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -56,7 +56,7 @@
        };
 
        pmu: pmu {
-               compatible = "arm,armv8-pmuv3";
+               compatible = "arm,cortex-a53-pmu";
                /* Recommendation from GIC500 TRM Table A.3 */
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
        };

diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index 66169bcf7c9a408e827dd21ffd51fe1617bd77d7..b7005b8031495e2e9fdff0396a883010eb902cf6 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -114,7 +114,7 @@
        };
 
        pmu: pmu {
-               compatible = "arm,armv8-pmuv3";
+               compatible = "arm,cortex-a72-pmu";
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
        };
 

diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index cc483f7344af3132aaa0059eb3e5b6c38ea19a5a..f0587fde147e6f87ceb98e728c396233a28d4053 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -115,7 +115,7 @@
        };
 
        pmu: pmu {
-               compatible = "arm,armv8-pmuv3";
+               compatible = "arm,cortex-a72-pmu";
                /* Recommendation from GIC500 TRM Table A.3 */
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
        };