ARM: dts: berlin: Align L2 cache-controller nodename with dtschema

Fix dtschema validator warnings like:
    l2-cache-controller@ac0000: $nodename:0:
        'l2-cache-controller@ac0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Link: https://lore.kernel.org/r/20200626080642.4244-1-krzk@kernel.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 3ab3cd250da705aadda3ac530677821802b88fda..6194857f8a02315c61c3586932c06e986cffa115 100644 (file)
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -106,7 +106,7 @@
                        status = "disabled";
                };
 
-               l2: l2-cache-controller@ac0000 {
+               l2: cache-controller@ac0000 {
                        compatible = "marvell,tauros3-cache", "arm,pl310-cache";
                        reg = <0xac0000 0x1000>;
                        cache-unified;

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 7cf3e6302d75c486147628f1adaf3b7c05e9979d..6f30d7eb3b4152175f6589875def72976b8f58a0 100644 (file)
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -71,7 +71,7 @@
                        status = "disabled";
                };
 
-               l2: l2-cache-controller@ac0000 {
+               l2: cache-controller@ac0000 {
                        compatible = "arm,pl310-cache";
                        reg = <0xac0000 0x1000>;
                        cache-unified;

diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index c44a32e873f44835aace8df9fd31ecab5f05f4a6..b6a0acac6836c523039775f73fbc729bf6cd1bee 100644 (file)
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -149,7 +149,7 @@
                        status = "disabled";
                };
 
-               l2: l2-cache-controller@ac0000 {
+               l2: cache-controller@ac0000 {
                        compatible = "arm,pl310-cache";
                        reg = <0xac0000 0x1000>;
                        cache-unified;