RDMA/hns: Modify the hop num of HIP09 EQ to 1

HIP09 EQ does not support level 2 addressing.

Link: https://lore.kernel.org/r/20211231101341.45759-3-liangwenpeng@huawei.com
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index 9b2fff2a027643701a0700c8605bd84a029d1981..f25a2036b6085267e2eb0f19f0dbd2408302fa81 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -2141,7 +2141,6 @@ static void apply_func_caps(struct hns_roce_dev *hr_dev)
        caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
        caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
 
-       caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
        caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
        caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
        caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
@@ -2158,6 +2157,7 @@ static void apply_func_caps(struct hns_roce_dev *hr_dev)
                                  (u32)priv->handle->rinfo.num_vectors - 2);
 
        if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
+               caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM;
                caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
                caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
 
@@ -2178,6 +2178,7 @@ static void apply_func_caps(struct hns_roce_dev *hr_dev)
        } else {
                u32 func_num = max_t(u32, 1, hr_dev->func_num);
 
+               caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM;
                caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
                caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
                caps->gid_table_len[0] /= func_num;

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index fddb9bc3c14cd2c5d62082046ca31097d95b88e9..e9a73c34389bd846c65e4aaff129eff81c1c910d 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@ -101,12 +101,14 @@
 #define HNS_ROCE_CQE_HOP_NUM                   1
 #define HNS_ROCE_SRQWQE_HOP_NUM                        1
 #define HNS_ROCE_PBL_HOP_NUM                   2
-#define HNS_ROCE_EQE_HOP_NUM                   2
 #define HNS_ROCE_IDX_HOP_NUM                   1
 #define HNS_ROCE_SQWQE_HOP_NUM                 2
 #define HNS_ROCE_EXT_SGE_HOP_NUM               1
 #define HNS_ROCE_RQWQE_HOP_NUM                 2
 
+#define HNS_ROCE_V2_EQE_HOP_NUM                        2
+#define HNS_ROCE_V3_EQE_HOP_NUM                        1
+
 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K       6
 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K                2
 #define HNS_ROCE_V2_GID_INDEX_NUM              16