MIPS: Loongson: Add Loongson-3A R3.1 basic support
authorHuacai Chen <chenhc@lemote.com>
Sat, 28 Apr 2018 03:21:25 +0000 (11:21 +0800)
committerPaul Burton <paul.burton@mips.com>
Tue, 24 Jul 2018 00:53:34 +0000 (17:53 -0700)
Loongson-3A R3.1 is the bugfix revision of Loongson-3A R3.

All Loongson-3 CPU family:

Code-name         Brand-name       PRId
Loongson-3A R1    Loongson-3A1000  0x6305
Loongson-3A R2    Loongson-3A2000  0x6308
Loongson-3A R3    Loongson-3A3000  0x6309
Loongson-3A R3.1  Loongson-3A3000  0x630d
Loongson-3B R1    Loongson-3B1000  0x6306
Loongson-3B R2    Loongson-3B1500  0x6307

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19263/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <james.hogan@mips.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhuacai@gmail.com>
arch/mips/include/asm/cpu.h
arch/mips/kernel/cpu-probe.c
arch/mips/loongson64/common/env.c
arch/mips/loongson64/loongson-3/smp.c
drivers/platform/mips/cpu_hwmon.c

index 5b9d02ef4f60375f9bf4370e12cd2e566890159b..dacbdb84516a09134896edd704d129b4f5f516f7 100644 (file)
  * Definitions for 7:0 on legacy processors
  */
 
-#define PRID_REV_TX4927                0x0022
-#define PRID_REV_TX4937                0x0030
-#define PRID_REV_R4400         0x0040
-#define PRID_REV_R3000A                0x0030
-#define PRID_REV_R3000         0x0020
-#define PRID_REV_R2000A                0x0010
-#define PRID_REV_TX3912                0x0010
-#define PRID_REV_TX3922                0x0030
-#define PRID_REV_TX3927                0x0040
-#define PRID_REV_VR4111                0x0050
-#define PRID_REV_VR4181                0x0050  /* Same as VR4111 */
-#define PRID_REV_VR4121                0x0060
-#define PRID_REV_VR4122                0x0070
-#define PRID_REV_VR4181A       0x0070  /* Same as VR4122 */
-#define PRID_REV_VR4130                0x0080
-#define PRID_REV_34K_V1_0_2    0x0022
-#define PRID_REV_LOONGSON1B    0x0020
-#define PRID_REV_LOONGSON1C    0x0020  /* Same as Loongson-1B */
-#define PRID_REV_LOONGSON2E    0x0002
-#define PRID_REV_LOONGSON2F    0x0003
-#define PRID_REV_LOONGSON3A_R1 0x0005
-#define PRID_REV_LOONGSON3B_R1 0x0006
-#define PRID_REV_LOONGSON3B_R2 0x0007
-#define PRID_REV_LOONGSON3A_R2 0x0008
-#define PRID_REV_LOONGSON3A_R3 0x0009
+#define PRID_REV_TX4927                        0x0022
+#define PRID_REV_TX4937                        0x0030
+#define PRID_REV_R4400                 0x0040
+#define PRID_REV_R3000A                        0x0030
+#define PRID_REV_R3000                 0x0020
+#define PRID_REV_R2000A                        0x0010
+#define PRID_REV_TX3912                        0x0010
+#define PRID_REV_TX3922                        0x0030
+#define PRID_REV_TX3927                        0x0040
+#define PRID_REV_VR4111                        0x0050
+#define PRID_REV_VR4181                        0x0050  /* Same as VR4111 */
+#define PRID_REV_VR4121                        0x0060
+#define PRID_REV_VR4122                        0x0070
+#define PRID_REV_VR4181A               0x0070  /* Same as VR4122 */
+#define PRID_REV_VR4130                        0x0080
+#define PRID_REV_34K_V1_0_2            0x0022
+#define PRID_REV_LOONGSON1B            0x0020
+#define PRID_REV_LOONGSON1C            0x0020  /* Same as Loongson-1B */
+#define PRID_REV_LOONGSON2E            0x0002
+#define PRID_REV_LOONGSON2F            0x0003
+#define PRID_REV_LOONGSON3A_R1         0x0005
+#define PRID_REV_LOONGSON3B_R1         0x0006
+#define PRID_REV_LOONGSON3B_R2         0x0007
+#define PRID_REV_LOONGSON3A_R2         0x0008
+#define PRID_REV_LOONGSON3A_R3_0       0x0009
+#define PRID_REV_LOONGSON3A_R3_1       0x000d
 
 /*
  * Older processors used to encode processor version and revision in two
index b2509c19cfb5b8cc7185f5cacadfc9f94c59fcbe..d535fc706a8b38a07c8e4c7de12ea111fcd95a60 100644 (file)
@@ -1849,7 +1849,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
                        set_elf_platform(cpu, "loongson3a");
                        set_isa(c, MIPS_CPU_ISA_M64R2);
                        break;
-               case PRID_REV_LOONGSON3A_R3:
+               case PRID_REV_LOONGSON3A_R3_0:
+               case PRID_REV_LOONGSON3A_R3_1:
                        c->cputype = CPU_LOONGSON3;
                        __cpu_name[cpu] = "ICT Loongson-3";
                        set_elf_platform(cpu, "loongson3a");
index 1e8a955ae5a820e37a5bdb23e970e6356693ccb9..8f68ee02a8c2447439c9b821f7f9835155333ac8 100644 (file)
@@ -198,7 +198,8 @@ void __init prom_init_env(void)
                        break;
                case PRID_REV_LOONGSON3A_R1:
                case PRID_REV_LOONGSON3A_R2:
-               case PRID_REV_LOONGSON3A_R3:
+               case PRID_REV_LOONGSON3A_R3_0:
+               case PRID_REV_LOONGSON3A_R3_1:
                        cpu_clock_freq = 900000000;
                        break;
                case PRID_REV_LOONGSON3B_R1:
index 8501109bb0f0f5bb70f7a4907431ff0c54c13e65..fea95d00326912ede09aba8f2c54d76ad9cfefcc 100644 (file)
@@ -682,7 +682,8 @@ void play_dead(void)
                        (void *)CKSEG1ADDR((unsigned long)loongson3a_r1_play_dead);
                break;
        case PRID_REV_LOONGSON3A_R2:
-       case PRID_REV_LOONGSON3A_R3:
+       case PRID_REV_LOONGSON3A_R3_0:
+       case PRID_REV_LOONGSON3A_R3_1:
                play_dead_at_ckseg1 =
                        (void *)CKSEG1ADDR((unsigned long)loongson3a_r2r3_play_dead);
                break;
index 322de58eebaf57a0d15690a5c0805209093f4c5b..f66521c7f8462b3ec438f1b07beae4f0efd487cc 100644 (file)
@@ -30,7 +30,8 @@ int loongson3_cpu_temp(int cpu)
        case PRID_REV_LOONGSON3B_R2:
                reg = ((reg >> 8) & 0xff) - 100;
                break;
-       case PRID_REV_LOONGSON3A_R3:
+       case PRID_REV_LOONGSON3A_R3_0:
+       case PRID_REV_LOONGSON3A_R3_1:
                reg = (reg & 0xffff)*731/0x4000 - 273;
                break;
        }