Blackfin: BF51x/BF52x: support GPIO Hysteresis/Schmitt Trigger options

Newer parts have optional Hysteresis/Schmitt Trigger options to help with
dirty signals.  So add some kconfig options for tuning this and enable it
by default for people.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index d37a397f43f5eacab8517c6c83fd2cf50e1905da..ac71dc15cbdb501d82e6c7fe1301ae738f444368 100644 (file)
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -864,6 +864,13 @@ void __init setup_arch(char **cmdline_p)
        bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
        bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
 #endif
+#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
+       bfin_write_PORTF_HYSTERISIS(HYST_PORTF_0_15);
+       bfin_write_PORTG_HYSTERISIS(HYST_PORTG_0_15);
+       bfin_write_PORTH_HYSTERISIS(HYST_PORTH_0_15);
+       bfin_write_MISCPORT_HYSTERISIS((bfin_read_MISCPORT_HYSTERISIS() &
+                                       ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
+#endif
 
        cclk = get_cclk();
        sclk = get_sclk();

diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
index 4ab2d166c83257f0068a0a5ecbf6a67fdeefcb48..1d9f631a7f949a915dad8e87ebb7c927ec793a8c 100644 (file)
--- a/arch/blackfin/mach-bf518/Kconfig
+++ b/arch/blackfin/mach-bf518/Kconfig
@@ -62,6 +62,67 @@ config BF518_UART1_PORTG
          PORT G
 endchoice
 
+comment "Hysteresis/Schmitt Trigger Control"
+config BFIN_HYSTERESIS_CONTROL
+       bool "Enable Hysteresis Control"
+       help
+         The ADSP-BF51x allows to control input hysteresis for Port F,
+         Port G and Port H and other processor signal inputs.
+         The Schmitt trigger enables can be set only for pin groups.
+         Saying Y will overwrite the default reset or boot loader
+         initialization.
+
+menu "PORT F"
+       depends on BFIN_HYSTERESIS_CONTROL
+config GPIO_HYST_PORTF_0_7
+       bool "Enable Hysteresis on PORTF {0...7}"
+config GPIO_HYST_PORTF_8_9
+       bool "Enable Hysteresis on PORTF {8, 9}"
+config GPIO_HYST_PORTF_10
+       bool "Enable Hysteresis on PORTF 10"
+config GPIO_HYST_PORTF_11
+       bool "Enable Hysteresis on PORTF 11"
+config GPIO_HYST_PORTF_12_13
+       bool "Enable Hysteresis on PORTF {12, 13}"
+config GPIO_HYST_PORTF_14_15
+       bool "Enable Hysteresis on PORTF {14, 15}"
+endmenu
+
+menu "PORT G"
+       depends on BFIN_HYSTERESIS_CONTROL
+config GPIO_HYST_PORTG_0
+       bool "Enable Hysteresis on PORTG 0"
+config GPIO_HYST_PORTG_1_4
+       bool "Enable Hysteresis on PORTG {1...4}"
+config GPIO_HYST_PORTG_5_6
+       bool "Enable Hysteresis on PORTG {5, 6}"
+config GPIO_HYST_PORTG_7_8
+       bool "Enable Hysteresis on PORTG {7, 8}"
+config GPIO_HYST_PORTG_9
+       bool "Enable Hysteresis on PORTG 9"
+config GPIO_HYST_PORTG_10
+       bool "Enable Hysteresis on PORTG 10"
+config GPIO_HYST_PORTG_11_13
+       bool "Enable Hysteresis on PORTG {11...13}"
+config GPIO_HYST_PORTG_14_15
+       bool "Enable Hysteresis on PORTG {14, 15}"
+endmenu
+
+menu "PORT H"
+       depends on BFIN_HYSTERESIS_CONTROL
+config GPIO_HYST_PORTH_0_7
+       bool "Enable Hysteresis on PORTH {0...7}"
+
+endmenu
+
+menu "None-GPIO"
+       depends on BFIN_HYSTERESIS_CONTROL
+config NONEGPIO_HYST_NMI_RST_BMODE
+       bool "Enable Hysteresis on {NMI, RESET, BMODE}"
+config NONEGPIO_HYST_JTAG
+       bool "Enable Hysteresis on JTAG"
+endmenu
+
 comment "Interrupt Priority Assignment"
 menu "Priority"
 

diff --git a/arch/blackfin/mach-bf518/include/mach/bf518.h b/arch/blackfin/mach-bf518/include/mach/bf518.h
index 856b330ecf0b3fcd08cacfd563b00389ce24b909..6906dee4f4cca032875301c627bd137d2dff6eb8 100644 (file)
--- a/arch/blackfin/mach-bf518/include/mach/bf518.h
+++ b/arch/blackfin/mach-bf518/include/mach/bf518.h
@@ -85,6 +85,111 @@
 
 #define AMGCTLVAL      (V_AMBEN | V_AMCKEN | V_CDPRIO)
 
+/**************************** Hysteresis Settings ****************************/
+
+#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
+#ifdef CONFIG_GPIO_HYST_PORTF_0_7
+#define HYST_PORTF_0_7         (1 << 0)
+#else
+#define HYST_PORTF_0_7         (0 << 0)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_8_9
+#define HYST_PORTF_8_9         (1 << 2)
+#else
+#define HYST_PORTF_8_9         (0 << 2)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_10
+#define HYST_PORTF_10          (1 << 4)
+#else
+#define HYST_PORTF_10          (0 << 4)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_11
+#define HYST_PORTF_11          (1 << 6)
+#else
+#define HYST_PORTF_11          (0 << 6)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_12_13
+#define HYST_PORTF_12_13       (1 << 8)
+#else
+#define HYST_PORTF_12_13       (0 << 8)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_14_15
+#define HYST_PORTF_14_15       (1 << 10)
+#else
+#define HYST_PORTF_14_15       (0 << 10)
+#endif
+
+#define HYST_PORTF_0_15        (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
+               HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
+
+#ifdef CONFIG_GPIO_HYST_PORTG_0
+#define HYST_PORTG_0           (1 << 0)
+#else
+#define HYST_PORTG_0           (0 << 0)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_1_4
+#define HYST_PORTG_1_4         (1 << 2)
+#else
+#define HYST_PORTG_1_4         (0 << 2)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_5_6
+#define HYST_PORTG_5_6         (1 << 4)
+#else
+#define HYST_PORTG_5_6         (0 << 4)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_7_8
+#define HYST_PORTG_7_8         (1 << 6)
+#else
+#define HYST_PORTG_7_8         (0 << 6)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_9
+#define HYST_PORTG_9           (1 << 8)
+#else
+#define HYST_PORTG_9           (0 << 8)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_10
+#define HYST_PORTG_10          (1 << 10)
+#else
+#define HYST_PORTG_10          (0 << 10)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_11_13
+#define HYST_PORTG_11_13       (1 << 12)
+#else
+#define HYST_PORTG_11_13       (0 << 12)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_14_15
+#define HYST_PORTG_14_15       (1 << 14)
+#else
+#define HYST_PORTG_14_15       (0 << 14)
+#endif
+
+#define HYST_PORTG_0_15        (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
+               HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
+               HYST_PORTG_11_13 | HYST_PORTG_14_15)
+
+#ifdef CONFIG_GPIO_HYST_PORTH_0_7
+#define HYST_PORTH_0_7         (1 << 0)
+#else
+#define HYST_PORTH_0_7         (0 << 0)
+#endif
+
+#define HYST_PORTH_0_15        (HYST_PORTH_0_7)
+
+#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
+#define HYST_NMI_RST_BMODE             (1 << 2)
+#else
+#define HYST_NMI_RST_BMODE             (0 << 2)
+#endif
+#ifdef CONFIG_NONEGPIO_HYST_JTAG
+#define HYST_JTAG                      (1 << 4)
+#else
+#define HYST_JTAG                      (0 << 4)
+#endif
+
+#define HYST_NONEGPIO  (HYST_NMI_RST_BMODE | HYST_JTAG)
+#define HYST_NONEGPIO_MASK             (0x3C)
+#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
+
 #ifdef CONFIG_BF518
 #define CPU "BF518"
 #define CPUID 0x27e8

diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
index 1f8cbe9d6b9ad22b190b233c961f78d067c1272a..0ba54701af0b9373ed156f9539646aa50eb06f77 100644 (file)
--- a/arch/blackfin/mach-bf527/Kconfig
+++ b/arch/blackfin/mach-bf527/Kconfig
@@ -79,6 +79,72 @@ config BF527_NAND_D_PORTH
          PORT H
 endchoice
 
+comment "Hysteresis/Schmitt Trigger Control"
+config BFIN_HYSTERESIS_CONTROL
+       bool "Enable Hysteresis Control"
+       help
+         The ADSP-BF52x allows to control input hysteresis for Port F,
+         Port G and Port H and other processor signal inputs.
+         The Schmitt trigger enables can be set only for pin groups.
+         Saying Y will overwrite the default reset or boot loader
+         initialization.
+
+menu "PORT F"
+       depends on BFIN_HYSTERESIS_CONTROL
+config GPIO_HYST_PORTF_0_7
+       bool "Enable Hysteresis on PORTF {0...7}"
+config GPIO_HYST_PORTF_8_9
+       bool "Enable Hysteresis on PORTF {8, 9}"
+config GPIO_HYST_PORTF_10
+       bool "Enable Hysteresis on PORTF 10"
+config GPIO_HYST_PORTF_11
+       bool "Enable Hysteresis on PORTF 11"
+config GPIO_HYST_PORTF_12_13
+       bool "Enable Hysteresis on PORTF {12, 13}"
+config GPIO_HYST_PORTF_14_15
+       bool "Enable Hysteresis on PORTF {14, 15}"
+endmenu
+
+menu "PORT G"
+       depends on BFIN_HYSTERESIS_CONTROL
+config GPIO_HYST_PORTG_0
+       bool "Enable Hysteresis on PORTG 0"
+config GPIO_HYST_PORTG_1_4
+       bool "Enable Hysteresis on PORTG {1...4}"
+config GPIO_HYST_PORTG_5_6
+       bool "Enable Hysteresis on PORTG {5, 6}"
+config GPIO_HYST_PORTG_7_8
+       bool "Enable Hysteresis on PORTG {7, 8}"
+config GPIO_HYST_PORTG_9
+       bool "Enable Hysteresis on PORTG 9"
+config GPIO_HYST_PORTG_10
+       bool "Enable Hysteresis on PORTG 10"
+config GPIO_HYST_PORTG_11_13
+       bool "Enable Hysteresis on PORTG {11...13}"
+config GPIO_HYST_PORTG_14_15
+       bool "Enable Hysteresis on PORTG {14, 15}"
+endmenu
+
+menu "PORT H"
+       depends on BFIN_HYSTERESIS_CONTROL
+config GPIO_HYST_PORTH_0_7
+       bool "Enable Hysteresis on PORTH {0...7}"
+config GPIO_HYST_PORTH_8
+       bool "Enable Hysteresis on PORTH 8"
+config GPIO_HYST_PORTH_9_15
+       bool "Enable Hysteresis on PORTH {9...15}"
+endmenu
+
+menu "None-GPIO"
+       depends on BFIN_HYSTERESIS_CONTROL
+config NONEGPIO_HYST_TMR0_FS1_PPICLK
+       bool "Enable Hysteresis on {TMR0, PPI_FS1, PPI_CLK}"
+config NONEGPIO_HYST_NMI_RST_BMODE
+       bool "Enable Hysteresis on {NMI, RESET, BMODE}"
+config NONEGPIO_HYST_JTAG
+       bool "Enable Hysteresis on JTAG"
+endmenu
+
 comment "Interrupt Priority Assignment"
 menu "Priority"
 

diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h
index ff68c889708785059fe1fded470556349f4369ef..8ff155b34f64844970dc9146cacb66237b21ee11 100644 (file)
--- a/arch/blackfin/mach-bf527/include/mach/bf527.h
+++ b/arch/blackfin/mach-bf527/include/mach/bf527.h
@@ -85,6 +85,126 @@
 
 #define AMGCTLVAL      (V_AMBEN | V_AMCKEN | V_CDPRIO)
 
+/**************************** Hysteresis Settings ****************************/
+
+#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
+#ifdef CONFIG_GPIO_HYST_PORTF_0_7
+#define HYST_PORTF_0_7         (1 << 0)
+#else
+#define HYST_PORTF_0_7         (0 << 0)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_8_9
+#define HYST_PORTF_8_9         (1 << 2)
+#else
+#define HYST_PORTF_8_9         (0 << 2)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_10
+#define HYST_PORTF_10          (1 << 4)
+#else
+#define HYST_PORTF_10          (0 << 4)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_11
+#define HYST_PORTF_11          (1 << 6)
+#else
+#define HYST_PORTF_11          (0 << 6)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_12_13
+#define HYST_PORTF_12_13       (1 << 8)
+#else
+#define HYST_PORTF_12_13       (0 << 8)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_14_15
+#define HYST_PORTF_14_15       (1 << 10)
+#else
+#define HYST_PORTF_14_15       (0 << 10)
+#endif
+
+#define HYST_PORTF_0_15        (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
+               HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
+
+#ifdef CONFIG_GPIO_HYST_PORTG_0
+#define HYST_PORTG_0           (1 << 0)
+#else
+#define HYST_PORTG_0           (0 << 0)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_1_4
+#define HYST_PORTG_1_4         (1 << 2)
+#else
+#define HYST_PORTG_1_4         (0 << 2)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_5_6
+#define HYST_PORTG_5_6         (1 << 4)
+#else
+#define HYST_PORTG_5_6         (0 << 4)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_7_8
+#define HYST_PORTG_7_8         (1 << 6)
+#else
+#define HYST_PORTG_7_8         (0 << 6)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_9
+#define HYST_PORTG_9           (1 << 8)
+#else
+#define HYST_PORTG_9           (0 << 8)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_10
+#define HYST_PORTG_10          (1 << 10)
+#else
+#define HYST_PORTG_10          (0 << 10)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_11_13
+#define HYST_PORTG_11_13       (1 << 12)
+#else
+#define HYST_PORTG_11_13       (0 << 12)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_14_15
+#define HYST_PORTG_14_15       (1 << 14)
+#else
+#define HYST_PORTG_14_15       (0 << 14)
+#endif
+
+#define HYST_PORTG_0_15        (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
+               HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
+               HYST_PORTG_11_13 | HYST_PORTG_14_15)
+
+#ifdef CONFIG_GPIO_HYST_PORTH_0_7
+#define HYST_PORTH_0_7         (1 << 0)
+#else
+#define HYST_PORTH_0_7         (0 << 0)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTH_8
+#define HYST_PORTH_8           (1 << 2)
+#else
+#define HYST_PORTH_8           (0 << 2)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTH_9_15
+#define HYST_PORTH_9_15                (1 << 4)
+#else
+#define HYST_PORTH_9_15                (0 << 4)
+#endif
+
+#define HYST_PORTH_0_15        (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
+
+#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
+#define HYST_TMR0_FS1_PPICLK           (1 << 0)
+#else
+#define HYST_TMR0_FS1_PPICLK           (0 << 0)
+#endif
+#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
+#define HYST_NMI_RST_BMODE             (1 << 2)
+#else
+#define HYST_NMI_RST_BMODE             (0 << 2)
+#endif
+#ifdef CONFIG_NONEGPIO_HYST_JTAG
+#define HYST_JTAG                      (1 << 4)
+#else
+#define HYST_JTAG                      (0 << 4)
+#endif
+
+#define HYST_NONEGPIO  (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
+#define HYST_NONEGPIO_MASK             (0x3F)
+#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
+
 #ifdef CONFIG_BF527
 #define CPU "BF527"
 #define CPUID 0x27e0