phy: qcom-qmp: rename common registers

A plenty of DP PHY registers are common between V3 and V4. To simplify
V4 code, rename all common registers.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210331151614.3810197-5-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 854f6ff7faef7eedfed9a69df91698e731950078..e1dbc9d936e7f2401ea4c9ff2457e60a14dd23dc 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -3354,20 +3354,20 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
 {
        writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
               DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-              qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+              qphy->pcs + QSERDES_DP_PHY_PD_CTL);
 
        /* Turn on BIAS current for PHY/PLL */
        writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
               QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
               qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
 
-       writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+       writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
 
        writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
               DP_PHY_PD_CTL_LANE_0_1_PWRDN |
               DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
               DP_PHY_PD_CTL_DP_CLAMP_EN,
-              qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+              qphy->pcs + QSERDES_DP_PHY_PD_CTL);
 
        writel(QSERDES_V3_COM_BIAS_EN |
               QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
@@ -3375,16 +3375,16 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
               QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
               qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
 
-       writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);
-       writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
-       writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
-       writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);
-       writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);
-       writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);
-       writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);
-       writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);
-       writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);
-       writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);
+       writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
+       writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
+       writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
+       writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
+       writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
+       writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
+       writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
+       writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
+       writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
+       writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
        qphy->dp_aux_cfg = 0;
 
        writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
@@ -3494,9 +3494,9 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
         *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
         */
        val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-       writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+       writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
 
-       writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
+       writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
        writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
        writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
 
@@ -3526,11 +3526,11 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
        clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
        clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
 
-       writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
-       writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
-       writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
-       writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
-       writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+       writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
+       writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
+       writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
+       writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
+       writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
 
        writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
 
@@ -3541,7 +3541,7 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
                        10000))
                return -ETIMEDOUT;
 
-       writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+       writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
 
        if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
                        status,
@@ -3550,9 +3550,9 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
                        10000))
                return -ETIMEDOUT;
 
-       writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+       writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
        udelay(2000);
-       writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+       writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
 
        return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
                        status,
@@ -3574,7 +3574,7 @@ static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
        qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
        val = cfg1_settings[qphy->dp_aux_cfg];
 
-       writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
+       writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
 
        return 0;
 }
@@ -3922,7 +3922,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy)
 
        if (cfg->type == PHY_TYPE_DP) {
                /* Assert DP PHY power down */
-               writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+               writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
        } else {
                /* PHY reset */
                if (!cfg->no_pcs_sw_reset)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 71ce3aa174ae69fba4dc24ea9eb05cca004083fd..981d8ee891c04e90c52db3c032926b580a7ef323 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -349,13 +349,13 @@
 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4                0x5c
 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5                0x60
 
-/* Only for QMP V3 PHY - DP PHY registers */
-#define QSERDES_V3_DP_PHY_REVISION_ID0                 0x000
-#define QSERDES_V3_DP_PHY_REVISION_ID1                 0x004
-#define QSERDES_V3_DP_PHY_REVISION_ID2                 0x008
-#define QSERDES_V3_DP_PHY_REVISION_ID3                 0x00c
-#define QSERDES_V3_DP_PHY_CFG                          0x010
-#define QSERDES_V3_DP_PHY_PD_CTL                       0x018
+/* QMP PHY - DP PHY registers */
+#define QSERDES_DP_PHY_REVISION_ID0                    0x000
+#define QSERDES_DP_PHY_REVISION_ID1                    0x004
+#define QSERDES_DP_PHY_REVISION_ID2                    0x008
+#define QSERDES_DP_PHY_REVISION_ID3                    0x00c
+#define QSERDES_DP_PHY_CFG                             0x010
+#define QSERDES_DP_PHY_PD_CTL                          0x018
 # define DP_PHY_PD_CTL_PWRDN                           0x001
 # define DP_PHY_PD_CTL_PSR_PWRDN                       0x002
 # define DP_PHY_PD_CTL_AUX_PWRDN                       0x004
@@ -363,18 +363,19 @@
 # define DP_PHY_PD_CTL_LANE_2_3_PWRDN                  0x010
 # define DP_PHY_PD_CTL_PLL_PWRDN                       0x020
 # define DP_PHY_PD_CTL_DP_CLAMP_EN                     0x040
-#define QSERDES_V3_DP_PHY_MODE                         0x01c
-#define QSERDES_V3_DP_PHY_AUX_CFG0                     0x020
-#define QSERDES_V3_DP_PHY_AUX_CFG1                     0x024
-#define QSERDES_V3_DP_PHY_AUX_CFG2                     0x028
-#define QSERDES_V3_DP_PHY_AUX_CFG3                     0x02c
-#define QSERDES_V3_DP_PHY_AUX_CFG4                     0x030
-#define QSERDES_V3_DP_PHY_AUX_CFG5                     0x034
-#define QSERDES_V3_DP_PHY_AUX_CFG6                     0x038
-#define QSERDES_V3_DP_PHY_AUX_CFG7                     0x03c
-#define QSERDES_V3_DP_PHY_AUX_CFG8                     0x040
-#define QSERDES_V3_DP_PHY_AUX_CFG9                     0x044
+#define QSERDES_DP_PHY_MODE                            0x01c
+#define QSERDES_DP_PHY_AUX_CFG0                                0x020
+#define QSERDES_DP_PHY_AUX_CFG1                                0x024
+#define QSERDES_DP_PHY_AUX_CFG2                                0x028
+#define QSERDES_DP_PHY_AUX_CFG3                                0x02c
+#define QSERDES_DP_PHY_AUX_CFG4                                0x030
+#define QSERDES_DP_PHY_AUX_CFG5                                0x034
+#define QSERDES_DP_PHY_AUX_CFG6                                0x038
+#define QSERDES_DP_PHY_AUX_CFG7                                0x03c
+#define QSERDES_DP_PHY_AUX_CFG8                                0x040
+#define QSERDES_DP_PHY_AUX_CFG9                                0x044
 
+/* Only for QMP V3 PHY - DP PHY registers */
 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK           0x048
 # define PHY_AUX_STOP_ERR_MASK                         0x01
 # define PHY_AUX_DEC_ERR_MASK                          0x02