mfd: palmas: Assign the right powerhold mask for tps65917
authorKeerthy <j-keerthy@ti.com>
Tue, 24 Oct 2017 08:21:36 +0000 (13:51 +0530)
committerLee Jones <lee.jones@linaro.org>
Mon, 8 Jan 2018 11:03:34 +0000 (11:03 +0000)
The powerhold mask for TPS65917 is different when comapred to
the other palmas versions. Hence assign the right mask that enables
power off of tps65917 pmic correctly.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
drivers/mfd/palmas.c
include/linux/mfd/palmas.h

index 3922a93f9f92420ae9f81f0bcc9c514e80a1e726..663a2398b6b1c878929940c6256c226b75adeec2 100644 (file)
@@ -430,6 +430,7 @@ static void palmas_power_off(void)
 {
        unsigned int addr;
        int ret, slave;
+       u8 powerhold_mask;
        struct device_node *np = palmas_dev->dev->of_node;
 
        if (of_property_read_bool(np, "ti,palmas-override-powerhold")) {
@@ -437,8 +438,15 @@ static void palmas_power_off(void)
                                          PALMAS_PRIMARY_SECONDARY_PAD2);
                slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
 
+               if (of_device_is_compatible(np, "ti,tps65917"))
+                       powerhold_mask =
+                               TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK;
+               else
+                       powerhold_mask =
+                               PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK;
+
                ret = regmap_update_bits(palmas_dev->regmap[slave], addr,
-                               PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK, 0);
+                                        powerhold_mask, 0);
                if (ret)
                        dev_err(palmas_dev->dev,
                                "Unable to write PRIMARY_SECONDARY_PAD2 %d\n",
index 3c8568aa82a5de82e48d30b6ff7f5511e6bafc88..75e5c8ff85fcc1770305fb7eecc509eb81893d93 100644 (file)
@@ -3733,6 +3733,9 @@ enum usb_irq_events {
 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE                       0x01
 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT                 0x00
 
+/* POWERHOLD Mask field for PRIMARY_SECONDARY_PAD2 register */
+#define TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK            0xC
+
 /* Registers for function RESOURCE */
 #define TPS65917_REGEN1_CTRL                                   0x2
 #define TPS65917_PLLEN_CTRL                                    0x3