Merge tag 'v5.3-rc3' into drm-next-5.4

Linux 5.3-rc3

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --cc MAINTAINERS
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ec71e2a7d7b71c0af24f9e0a6f2818b3c5b06029,32773b7523d204a8b29266931fb4a9e577c571a4..43427a3148b74094c6b89c7514b6148b97b86801
--- 1/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
--- 2/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@@ -1581,27 -1441,17 +1581,36 @@@ static void gfx_v10_0_init_compute_vmid
        }
        nv_grbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+ 
+       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+          acccess. These should be enabled by FW for target VMIDs. */
+       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
+       }
  }
  
 +static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
 +{
 +      int vmid;
 +
 +      /*
 +       * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
 +       * access. Compute VMIDs should be enabled by FW for target VMIDs,
 +       * the driver can enable them for graphics. VMID0 should maintain
 +       * access so that HWS firmware can save/restore entries.
 +       */
 +      for (vmid = 1; vmid < 16; vmid++) {
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
 +      }
 +}
 +
 +
  static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
  {
        int i, j, k;

diff --cc drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 53eee129b168132ed5914144e17ee3f71a9ec6cf,21187275dfd37e496db7de2de3f21f2518a606f9..791ba398f007ef17e1330fd6160ba69d7f7d0043
--- 1/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
--- 2/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@@ -1879,26 -1879,17 +1879,35 @@@ static void gfx_v7_0_init_compute_vmid(
        }
        cik_srbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+ 
+       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+          acccess. These should be enabled by FW for target VMIDs. */
+       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+               WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
+               WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
+               WREG32(amdgpu_gds_reg_offset[i].gws, 0);
+               WREG32(amdgpu_gds_reg_offset[i].oa, 0);
+       }
  }
  
 +static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
 +{
 +      int vmid;
 +
 +      /*
 +       * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
 +       * access. Compute VMIDs should be enabled by FW for target VMIDs,
 +       * the driver can enable them for graphics. VMID0 should maintain
 +       * access so that HWS firmware can save/restore entries.
 +       */
 +      for (vmid = 1; vmid < 16; vmid++) {
 +              WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
 +              WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
 +              WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
 +              WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
 +      }
 +}
 +
  static void gfx_v7_0_config_init(struct amdgpu_device *adev)
  {
        adev->gfx.config.double_offchip_lds_buf = 1;

diff --cc drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 3f866107d38335754814b999c6c38b548e1bab23,751567f78567357c0099cf426c550fe7d9d72b3f..87dd55e9d72b2fe7d8323f8fef33e9024b2fc03d
--- 1/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
--- 2/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@@ -3739,26 -3706,17 +3739,35 @@@ static void gfx_v8_0_init_compute_vmid(
        }
        vi_srbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+ 
+       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+          acccess. These should be enabled by FW for target VMIDs. */
+       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+               WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
+               WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
+               WREG32(amdgpu_gds_reg_offset[i].gws, 0);
+               WREG32(amdgpu_gds_reg_offset[i].oa, 0);
+       }
  }
  
 +static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
 +{
 +      int vmid;
 +
 +      /*
 +       * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
 +       * access. Compute VMIDs should be enabled by FW for target VMIDs,
 +       * the driver can enable them for graphics. VMID0 should maintain
 +       * access so that HWS firmware can save/restore entries.
 +       */
 +      for (vmid = 1; vmid < 16; vmid++) {
 +              WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
 +              WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
 +              WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
 +              WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
 +      }
 +}
 +
  static void gfx_v8_0_config_init(struct amdgpu_device *adev)
  {
        switch (adev->asic_type) {

diff --cc drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 0951b91180c424b56aa0bb5edbcb83530ee775e3,1cf639a511783c9cb1280f86a6ddbc3a5577c349..52a6fd12e26655fd50731d864c0d8101113ceeff
--- 1/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
--- 2/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@@ -2405,26 -1918,17 +2405,35 @@@ static void gfx_v9_0_init_compute_vmid(
        }
        soc15_grbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+ 
+       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+          acccess. These should be enabled by FW for target VMIDs. */
+       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
+       }
  }
  
 +static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
 +{
 +      int vmid;
 +
 +      /*
 +       * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
 +       * access. Compute VMIDs should be enabled by FW for target VMIDs,
 +       * the driver can enable them for graphics. VMID0 should maintain
 +       * access so that HWS firmware can save/restore entries.
 +       */
 +      for (vmid = 1; vmid < 16; vmid++) {
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
 +      }
 +}
 +
  static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
  {
        u32 tmp;

diff --cc drivers/gpu/drm/amd/amdkfd/kfd_crat.c
Simple merge

diff --cc drivers/gpu/drm/ttm/ttm_bo.c
Simple merge

diff --cc include/drm/ttm/ttm_bo_driver.h
Simple merge