Merge patch "riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=y"

This is a single fix, but it conflicts with some recent features.  I'm
merging it on top of the commit it fixes to ease backporting.

* b4-shazam-merge:
  riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=y

Link: https://lore.kernel.org/r/20220922060958.44203-1-samuel@sholland.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --cc arch/riscv/include/asm/hwcap.h
index 86328e3acb02ee3b5752642039c2cdd2806989a1,3bf10a8e665af4340d01803d8c8bf64a5ff5c431..64ad1937e71494b17389697549fcec5cade84939
--- 1/arch/riscv/include/asm/hwcap.h
--- 2/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@@ -70,8 -67,6 +70,7 @@@ static_assert(RISCV_ISA_EXT_ID_MAX <= R
   */
  enum riscv_isa_ext_key {
        RISCV_ISA_EXT_KEY_FPU,          /* For 'F' and 'D' */
-       RISCV_ISA_EXT_KEY_ZIHINTPAUSE,
 +      RISCV_ISA_EXT_KEY_SVINVAL,
        RISCV_ISA_EXT_KEY_MAX,
  };
  
@@@ -91,10 -86,6 +90,8 @@@ static __always_inline int riscv_isa_ex
                return RISCV_ISA_EXT_KEY_FPU;
        case RISCV_ISA_EXT_d:
                return RISCV_ISA_EXT_KEY_FPU;
-       case RISCV_ISA_EXT_ZIHINTPAUSE:
-               return RISCV_ISA_EXT_KEY_ZIHINTPAUSE;
 +      case RISCV_ISA_EXT_SVINVAL:
 +              return RISCV_ISA_EXT_KEY_SVINVAL;
        default:
                return -EINVAL;
        }

diff --cc arch/riscv/include/asm/vdso/processor.h
index fa70cfe507aa118260d1d751cc1b7658fa739349,789bdb8211a25604be9df9200601edc75907f806..14f5d27783b85811a4f7e6e1d43c9b5ee9aca5a1
--- 1/arch/riscv/include/asm/vdso/processor.h
--- 2/arch/riscv/include/asm/vdso/processor.h
+++ b/arch/riscv/include/asm/vdso/processor.h
@@@ -9,25 -8,21 +8,22 @@@
  
  static inline void cpu_relax(void)
  {
-       if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) {
  #ifdef __riscv_muldiv
-               int dummy;
-               /* In lieu of a halt instruction, induce a long-latency stall. */
-               __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
+       int dummy;
+       /* In lieu of a halt instruction, induce a long-latency stall. */
+       __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
  #endif
-       } else {
-               /*
-                * Reduce instruction retirement.
-                * This assumes the PC changes.
-                */
- #ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
-               __asm__ __volatile__ ("pause");
++
++#ifdef __riscv_zihintpause
+       /*
+        * Reduce instruction retirement.
+        * This assumes the PC changes.
+        */
 -#ifdef __riscv_zihintpause
+       __asm__ __volatile__ ("pause");
  #else
-               /* Encoding of the pause instruction */
-               __asm__ __volatile__ (".4byte 0x100000F");
+       /* Encoding of the pause instruction */
+       __asm__ __volatile__ (".4byte 0x100000F");
  #endif
-       }
        barrier();
  }