ARM: dts: sunxi: Switch to the generic PHY properties
authorMaxime Ripard <maxime.ripard@bootlin.com>
Thu, 6 Jun 2019 19:21:09 +0000 (21:21 +0200)
committerMaxime Ripard <maxime.ripard@bootlin.com>
Mon, 22 Jul 2019 07:41:09 +0000 (09:41 +0200)
The DWMAC specific properties to manage the PHY have been superseeded by
the generic PHY properties. Let's move to it.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
arch/arm/boot/dts/sun6i-a31-hummingbird.dts
arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
arch/arm/boot/dts/sun7i-a20-hummingbird.dts
arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts

index 09832b4e8fc8544574256e0bb96d3351f5ac4c2c..2652d737fe7c230af3afe70283fb1765bbdff27c 100644 (file)
        pinctrl-0 = <&gmac_rgmii_pins>;
        phy = <&phy1>;
        phy-mode = "rgmii";
-       snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>;
-       snps,reset-active-low;
-       snps,reset-delays-us = <0 10000 30000>;
        status = "okay";
 
        phy1: ethernet-phy@1 {
                reg = <1>;
+               reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>;
+               reset-assert-us = <10000>;
+               reset-deassert-us = <30000>;
        };
 };
 
index 8e724c52feffeccaab0a5c25afcc6638d91de67a..7899712400b2bbc362aa75ccf12cc0d3c125de7d 100644 (file)
        phy = <&phy1>;
        phy-mode = "rgmii";
        phy-supply = <&reg_dldo1>;
-       snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
-       snps,reset-active-low;
-       snps,reset-delays-us = <0 10000 30000>;
        status = "okay";
 
        phy1: ethernet-phy@1 {
                reg = <1>;
+               reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>; /* PA21 */
+               reset-assert-us = <10000>;
+               reset-deassert-us = <30000>;
        };
 };
 
index fd0153f65685618edacc77875d49fb558e3f9f4e..b01d91d025ecb280e54cefa548b495911003c2bc 100644 (file)
        phy = <&phy1>;
        phy-mode = "rgmii";
        phy-supply = <&reg_gmac_vdd>;
-       /* phy reset config */
-       snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
-       snps,reset-active-low;
-       /* wait 1s after reset, otherwise fail to read phy id */
-       snps,reset-delays-us = <0 10000 1000000>;
        status = "okay";
 
        phy1: ethernet-phy@1 {
                reg = <1>;
+               reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
+               reset-assert-us = <10000>;
+               /* wait 1s after reset, otherwise fail to read phy id */
+               reset-deassert-us = <1000000>;
        };
 };
 
index c34a83f666c72e2a61a24de9ac772e8e8ca48d47..ca12cee2707238d7a7e7a805060f26407f81fef1 100644 (file)
        phy = <&phy3>;
        phy-mode = "rgmii";
        phy-supply = <&reg_vcc3v3>;
-
-       snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>;
-       snps,reset-active-low;
-       snps,reset-delays-us = <0 10000 1000000>;
        status = "okay";
 
        phy3: ethernet-phy@3 {
                reg = <3>;
+               reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
+               reset-assert-us = <10000>;
+               /* wait 1s after reset, otherwise fail to read phy id */
+               reset-deassert-us = <1000000>;
        };
 };