Merge tag 'gvt-fixes-2018-11-26' of https://github.com/intel/gvt-linux into drm-intel...

gvt-fixes-2018-11-26

- Fix engine check for correct MOCS regs load (Xinyun)
- Fix rpm locking for vGPU ggtt init (Henry)
- Fix use-after-free when destroy partial ggtt entries (Chris)

Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181126021820.GL12743@zhen-hp.sh.intel.com

diff --combined drivers/gpu/drm/i915/gvt/gtt.c
index 58e166effa456426d7fe2ee4f059a0533b4bfe0c,3b32e69beac670d5031295bd4a0662fa7e431a9e..c7103dd2d8d571fde462f173dcc67efc0973cc69
--- 1/drivers/gpu/drm/i915/gvt/gtt.c
--- 2/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@@ -1113,10 -1113,6 +1113,10 @@@ static inline void ppgtt_generate_shado
  }
  
  /**
 + * Check if can do 2M page
 + * @vgpu: target vgpu
 + * @entry: target pfn's gtt entry
 + *
   * Return 1 if 2MB huge gtt shadowing is possilbe, 0 if miscondition,
   * negtive if found err.
   */
@@@ -1947,7 -1943,7 +1947,7 @@@ void intel_vgpu_unpin_mm(struct intel_v
  
  /**
   * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
 - * @vgpu: a vGPU
 + * @mm: target vgpu mm
   *
   * This function is called when user wants to use a vGPU mm object. If this
   * mm object hasn't been shadowed yet, the shadow will be populated at this
@@@ -2447,10 -2443,11 +2447,11 @@@ static void intel_vgpu_destroy_all_ppgt
  
  static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
  {
-       struct intel_gvt_partial_pte *pos;
+       struct intel_gvt_partial_pte *pos, *next;
  
-       list_for_each_entry(pos,
-                       &vgpu->gtt.ggtt_mm->ggtt_mm.partial_pte_list, list) {
+       list_for_each_entry_safe(pos, next,
+                                &vgpu->gtt.ggtt_mm->ggtt_mm.partial_pte_list,
+                                list) {
                gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
                        pos->offset, pos->data);
                kfree(pos);
@@@ -2526,7 -2523,8 +2527,7 @@@ fail
  /**
   * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
   * @vgpu: a vGPU
 - * @page_table_level: PPGTT page table level
 - * @root_entry: PPGTT page table root pointers
 + * @pdps: pdp root array
   *
   * This function is used to find a PPGTT mm object from mm object pool
   *

diff --combined drivers/gpu/drm/i915/gvt/mmio_context.c
index 36a5147cd01e5224b2c6563c29128d05688e7fba,cdd366d44938b135debd6f461fbe88748246342f..d6e02c15ef97d995fd4ec2ab203c15e5ff8ab245
--- 1/drivers/gpu/drm/i915/gvt/mmio_context.c
--- 2/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@@ -37,6 -37,19 +37,6 @@@
  #include "gvt.h"
  #include "trace.h"
  
 -/**
 - * Defined in Intel Open Source PRM.
 - * Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms
 - */
 -#define TRVATTL3PTRDW(i)      _MMIO(0x4de0 + (i)*4)
 -#define TRNULLDETCT           _MMIO(0x4de8)
 -#define TRINVTILEDETCT                _MMIO(0x4dec)
 -#define TRVADR                        _MMIO(0x4df0)
 -#define TRTTE                 _MMIO(0x4df4)
 -#define RING_EXCC(base)               _MMIO((base) + 0x28)
 -#define RING_GFX_MODE(base)   _MMIO((base) + 0x29c)
 -#define VF_GUARDBAND          _MMIO(0x83a4)
 -
  #define GEN9_MOCS_SIZE                64
  
  /* Raw offset is appened to each line for convenience. */
@@@ -158,6 -171,8 +158,8 @@@ static void load_render_mocs(struct drm
        int ring_id, i;
  
        for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) {
+               if (!HAS_ENGINE(dev_priv, ring_id))
+                       continue;
                offset.reg = regs[ring_id];
                for (i = 0; i < GEN9_MOCS_SIZE; i++) {
                        gen9_render_mocs.control_table[ring_id][i] =